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GeodeTM CS5530A I/O Companion Multi-Function South Bridge
May 2001 Revision 1.1
GeodeTM CS5530A I/O Companion Multi-Function South Bridge
General Description
The CS5530A I/O companion is designed to work in conjunction with a GX-series processor (i.e., GX1, GXLV, GXm); all members of the National Semiconductor(R) GeodeTM family of products. Together, the Geode processor and CS5530A provide a system-level solution well suited for the high performance needs of a host of devices which include digital set-top boxes and thin client devices. Due to the low power consumption of the GX-series processors, this solution satisfies the needs of battery powered devices such as National's WebPADTM system, and thermal design is eased allowing for fanless system design. The CS5530A I/O companion is a PCI-to-ISA bridge (South Bridge), ACPI-compliant chipset that provides AT/ISA style functionality. The device contains state-of-the-art power management that enables systems, especially battery powered systems, to significantly reduce power consumption. Audio is supported through PCI bus master engines which connect to an AC97 compatible codec such as the National Semiconductor LM4548. If industry standard audio is required, a combination of hardware and software called Virtual System Architecture(R) (VSATM) technology is provided. The Geode GX-series processors' graphics/video output is connected to the CS5530A. The CS5530A graphics/video support includes a PLL that generates the DOT clock for the GX-series processors (where the graphics controller is located), video acceleration hardware, gamma RAM plus three DACs for RGB output to CRT, and digital RGB that can be directly connected to TFT panels or NTSC/PAL encoders. The digital RGB output can also be connected to the National Semiconductor Geode CS9211 graphics companion (a flat panel display controller) for DSTN panel support.
GeodeTM CS5530A Internal Block Diagram
PCI Bus
USB PCI to USB Macro GPIOs GPCS Pwr Mgmt, Traps, Events, and Timers PCI to X-Bus / X-Bus to PCI Bridge CS5530A Support PCI Configuration Registers Active Decode Address Mapper X-Bus Arbiter
X-Bus
Graphics and Video from CPU
Display Interface MPEG, DOT Clock CSC and SCL RGB/FP Interface
AT Compatibility Logic
Audio/Codec/MPU Interface
Display
GeodeTM CS9211 Graphics Companion Joystick
ISA Bus Interface AT Ports, ISA Megacells
Ultra DMA/33 IDE Interface
AC97 Codec (e.g., LM4548)
Joystick / Game Port ISA Bus PC97317 SIO IDE
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, VSA and WebPAD are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
(c) 2001 National Semiconductor Corporation
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GeodeTM CS5530A
Designed for use with National's Geode GX-series processors 352 PBGA (Plastic Ball Grid Array) package 3.3V or 5.0V PCI bus compatible 5.0V tolerant on all inputs 3.3V core
PCI-to-ISA Bridge PCI 2.1 compliant Supports PCI initiator-to-ISA and ISA master-to-PCI cycle translations PCI master for audio I/O and IDE controllers Subtractive agent for unclaimed transactions PCI-to-ISA interrupt mapper/translator
AT Compatibility
8254-equivalent timer Two 8237-equivalent DMA controllers Boot ROM and keyboard chip select Extended ROM to 16 MB
Bus Mastering IDE Controllers Two controllers with support for up to four IDE devices Independent timing for master and slave devices for both channels PCI bus master burst reads and writes Ultra DMA/33 (ATA-4) support Multiword DMA support Programmed I/O (PIO) Modes 0-4 support
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Two 8259A-equivalent interrupt controllers
General Features
Features

Two bus mastering IDE controllers are included for support of up to four ATA-compliant devices. A two-port Universal Serial Bus (USB) provides high speed, Plug & Play expansion for a variety of consumer peripheral devices such as a keyboard, mouse, printer, and digital camera. If additional functions are required like real-time clock, floppy disk, PS2 keyboard, and PS2 mouse, a SuperI/O such as the National PC97317 can be easily connected to the CS5530A.
Power Management Intelligent system controller supports multiple power management standards: -- Full ACPI and Legacy (APM) support -- Directly manages all GX-series processors' power states (including automatic Suspend modulation for optimal performance/thermal balancing) I/O traps and idle timers for peripheral power management Up to eight GPIOs for system control: -- All eight are configurable as external wakeup events Dedicated inputs for keyboard and mouse wakeup events

XpressAUDIO Provides "back-end" hardware support via six buffered PCI bus masters AC97 codec interface: -- Specification Revision 1.3, 2.0, and 2.1 compliant interface. Note that the codec (e.g., LM4548) must have SRC (sample rate conversion) support
Display Subsystem Extensions Complements the GX-series processors' graphics and video capabilities: -- Three independent line buffers for accelerating video data streams -- Handles asynchronous video and graphics data streams concurrently from the processor -- YUV to RGB conversion hardware -- Arbitrary X & Y interpolative scaling -- Color keying for graphics/video overlay VDACs / Display interface: -- Three integrated DACs -- Gamma RAM: - Provides gamma correction for graphics data streams - Provides brightness/contrast correction for video data streams -- Integrated DOT clock generator -- Digital RGB interface drives TFT panels or standard NTSC/PAL encoders -- Up to 1280x1024 @ 85 Hz
Universal Serial Bus Two independent USB interfaces: -- Open Host Controller Interface (OpenHCI) specification compliant -- Second generation proven core design
Revision 1.1
GeodeTM CS5530A
Table of Contents
1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 1.2 1.3 PCI BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AT COMPATIBILITY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.2 Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.3 Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IDE CONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.1 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 XPRESSAUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6.1 AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6.2 VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DISPLAY SUBSYSTEM EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 UNIVERSAL SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PROCESSOR SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 1.5 1.6
1.7 1.8 1.9 1.10
2.0
Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 2.2 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.1 Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.2 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.3 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.4 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.5 ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.6 ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.7 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.8 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.9 Game Port and General Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.10 Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.11 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.12 DCLK PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.13 Power, Ground, and No Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.14 Internal Test and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1 PROCESSOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.1 Display Subsystem Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.2 PSERIAL Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1.2.1 Video Retrace Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2
PCI BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.1 PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.2 PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.3 Special Bus Cycles-Shutdown/Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.4 PCI Bus Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.5 PCI Interrupt Routing Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.6 Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision 1.1
3
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GeodeTM CS5530A
Table of Contents (Continued)
3.3 RESETS AND CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.2 ISA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.3 DOT Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.3.1 DCLK Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.1 CPU Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.1.1 3.4.1.2 3.4.1.3 3.4.1.4 3.4.1.5 3.4.1.6 3.4.1.7 On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Active Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Suspend Modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Save-to-Disk/Save-to-RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.4.2 3.4.3
APM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Peripheral Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.3.1 3.4.3.2 3.4.3.3 3.4.3.4 3.4.3.5 3.4.3.6 Device Idle Timers and Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 General Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ACPI Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 General Purpose I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Power Management SMI Status Reporting Registers . . . . . . . . . . . . . . . . . . . . . . . . 78 Device Power Management Register Programming Summary . . . . . . . . . . . . . . . . . 86
3.5
PC/AT COMPATIBILITY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.5.1 ISA Subtractive Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.5.2 ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.5.2.1 3.5.2.2 3.5.2.3 3.5.2.4 3.5.2.5 Delayed PCI Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Limited ISA and ISA Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ISA Bus Data Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I/O Recovery Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ISA DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.5.3 3.5.4
ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Megacells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.5.4.1 3.5.4.2 3.5.4.3 3.5.4.4 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PCI Compatible Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I/O Port 092h System Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I/O Port 061h System Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Fast Keyboard Gate Address 20 and CPU Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.5.5
I/O Ports 092h and 061h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.5.5.1 3.5.5.2 3.5.5.3
3.5.6
Keyboard Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.5.6.1
3.6
3.5.7 External Real-Time Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 IDE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.6.1 IDE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.6.2 IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.6.2.1 3.6.2.2 3.6.2.3 PIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Ultra DMA/33 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Revision 1.1
GeodeTM CS5530A
Table of Contents (Continued)
3.7 XPRESSAUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3.7.1 Subsystem Data Transport Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.7.1.1 3.7.1.2 3.7.1.3 3.7.1.4 3.7.1.5 Audio Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Physical Region Descriptor Table Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Physical Region Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VSA Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Audio SMI Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 IRQ Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.7.2
VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.7.2.1 3.7.2.2 3.7.2.3
3.8
DISPLAY SUBSYSTEM EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.8.1 Video Interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.8.2 Video Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
3.8.2.1 3.8.2.2 3.8.2.3 3.8.2.4 3.8.2.5 Line Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Video Port Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Video Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 X and Y Scaler / Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Color-Space-Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
3.8.3 3.8.4 3.8.5
Video Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Gamma RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.8.5.1 3.8.5.2 3.8.5.3 Video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 VESA DDC2B / DPMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Flat Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.9
UNIVERSAL SERIAL BUS SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.9.1 USB PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.9.2 USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.9.3 USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.0
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.1 4.2 4.3 PCI CONFIGURATION SPACE AND ACCESS METHODS . . . . . . . . . . . . . . . . . . . . . . . . . 141 REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 CHIPSET REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.3.1 Bridge Configuration Registers - Function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.3.2 SMI Status and ACPI Timer Registers - Function 1 . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.3.3 IDE Controller Registers - Function 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.3.4 XpressAUDIO Registers - Function 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.3.5 Video Controller Registers - Function 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 USB REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 CS5530A ISA LEGACY I/O REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 V-ACPI I/O REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
4.4 4.5 4.6
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Table of Contents (Continued) 5.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
5.1 ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.1.1 Pull-Up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.1.2 Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.1.3 NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.1.4 Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 5.4.1 Definition of System Conditions for Measuring "On" Parameters . . . . . . . . . . . . . . . 240 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 DISPLAY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
5.2 5.3 5.4 5.5 5.6
6.0
Test Mode Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.1 6.2 NAND TREE TEST MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 I/O TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
7.0
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Appendix A
A.1
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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Architecture Overview
For CPU interface connection refer to Figure 1-5 "Example System Block Diagram" on page 12.
The Geode CS5530A can be described as providing the functional blocks shown in Figure 1-1. * PCI bus master/slave interface * ISA bus interface * AT compatibility logic * IDE controllers * Power management -- GPIO interfaces -- Traps, Events, Timers * Joystick/Game Port interface * Virtual audio support hardware * Video display, which includes MPEG accelerator, RAMDAC, and video ports * USB controller
1.1
PCI BUS INTERFACE
The CS5530A provides a PCI bus interface that is both a slave for PCI cycles initiated by the CPU or other PCI master devices, and a non-preemptable master for DMA transfer cycles. The chip also is a standard PCI master for the IDE controllers and audio I/O logic. The CS5530A supports positive decode for configurable memory and I/O regions and implements a subtractive decode option for unclaimed PCI accesses. The CS5530A also generates address and data parity and performs parity checking. The CS5530A does not include the PCI bus arbiter, which is located in the processor. Configuration registers are accessed through the PCI interface using the PCI Bus Type 1 configuration mechanism as described in the PCI 2.1 Specification.
PCI Bus
USB PCI to USB Macro GPIOs GPCS Pwr Mgmt, Traps, Events, and Timers PCI to X-Bus / X-Bus to PCI Bridge CS5530A Support PCI Configuration Registers Active Decode Address Mapper X-Bus Arbiter
X-Bus
Graphics and Video from CPU
Display Interface MPEG, DOT Clock CSC and SCL RGB/FP Interface
AT Compatibility Logic
Audio/Codec/MPU Interface
Display
GeodeTM CS9211 Graphics Companion Joystick
ISA Bus Interface AT Ports, ISA Megacells
Ultra DMA/33 IDE Interface
AC97 Codec (e.g., LM4548)
Joystick / Game Port ISA Bus PC97317 SIO IDE
Figure 1-1. Internal Block Diagram
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Architecture Overview (Continued)
1.2 ISA BUS INTERFACE
1.3.1 DMA Controller The CS5530A supports the industry standard DMA architecture using two 8237-compatible DMA controllers in cascaded configuration. CS5530A-supported DMA functions include: * Standard seven-channel DMA support * 32-bit address range support via high page registers * IOCHRDY extended cycles for compatible timing transfers * ISA bus master device support using cascade mode 1.3.2 Programmable Interval Timer The CS5530A contains an 8254-equivalent programmable interval timer. This device has three timers, each with an input frequency of 1.193 MHz. 1.3.3 Programmable Interrupt Controller The CS5530A contains two 8259-equivalent programmable interrupt controllers (PICs), with eight interrupt request lines each, for a total of 16 interrupts. The two controllers are cascaded internally, and two of the interrupt request inputs are connected to the internal circuitry. This allows a total of 13 externally available interrupt requests. Each CS5530A IRQ signal can be individually selected as edge- or level-sensitive. The PCI interrupt signals are routed internally to the PICs IRQs. The CS5530A provides an ISA bus interface for unclaimed memory and I/O cycles on PCI. The CS5530A is the default subtractive decoding agent and forwards all unclaimed memory and I/O cycles to the ISA interface; however, the CS5530A may be configured to ignore either I/O, memory, or all unclaimed cycles (subtractive decode disabled). The CS5530A supports two modes on the ISA interface. The default mode, Limited ISA Mode, supports the full memory and I/O address range without ISA mastering. The address and data buses are multiplexed together, requiring an external latch to latch the lower 16 bits of address of the ISA cycle. The signal SA_LATCH is generated when the data on the SA/SD bus is a valid address. Additionally, the upper four address bits, SA[23:20], are multiplexed on GPIO[7:4]. The second mode, ISA Master Mode, supports ISA bus masters and requires no external circuitry. When the CS5530A is placed in ISA Master Mode, a large number of pins are redefined. In this mode, the CS5530A cannot support TFT flat panels or TV controllers since most of the signals used to support these functions have been redefined. This mode is required if ISA slots or ISA masters are used. ISA master cycles are only passed to the PCI bus if they access memory. I/O accesses are left to complete on the ISA bus. For further information regarding mode selection and operational details refer to Section 3.5.2.2 "Limited ISA and ISA Master Modes" on page 90.
1.4
IDE CONTROLLERS
1.3
AT COMPATIBILITY LOGIC
The CS5530A integrates: * Two 8237-equivalent DMA controllers with full 32-bit addressing * Two 8259-equivalent interrupt controllers providing 13 individually programmable external interrupts * An 8254-equivalent timer for refresh, timer, and speaker logic * NMI control and generation for PCI system errors and all parity errors * Support for standard AT keyboard controllers * Positive decode for the AT I/O register space * Reset control
The CS5530A integrates two PCI bus mastering, ATA-4 compatible IDE controllers. These controllers support Ultra DMA/33 (enabled in Microsoft Windows 95 and Windows NT by using a driver provided by National Semiconductor), Multiword DMA, and Programmed I/O (PIO) modes. Two devices are supported on each controller. The data-transfer speed for each device on each controller can be independently programmed. This allows high-speed IDE peripherals to coexist on the same channel as lower speed devices. Faster devices must be ATA-4 compatible.
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Architecture Overview (Continued)
1.5 POWER MANAGEMENT 1.6 XPRESSAUDIO
The CS5530A integrates advanced power management features including: * Idle timers for common system peripherals * Address trap registers for programmable address ranges for I/O or memory accesses * Up to eight programmable GPIOs * Clock throttling with automatic speedup for the CPU clock * Software CPU stop clock * Save-to-Disk/RAM with peripheral shadow registers * Dedicated serial bus to/from the GX-series processor providing CPU power management status The CS5530A is an ACPI (Advanced Control and Power Interface) compliant chipset. An ACPI compliant system is one whose underlying BIOS, device drivers, chipset and peripherals conform to revision 1.0 or newer of the ACPI specification. The "Fixed Feature" and "General Purpose" registers are virtual. They are emulated by the SMI handling code rather than existing in physical hardware. To the ACPI compliant operating system, the SMI-base virtualization is transparent; however, to eliminate unnecessary latencies, the ACPI timer exists in physical hardware. The CS5530A V-ACPI (Virtual ACPI) solution provides the following support: * CPU States -- C1, C2 * Sleep States -- S1, S2, S4, S4BIOS, S5 * Embedded Controller (Optional) -- SCI and SWI event inputs. * General Purpose Events -- Fully programmable GPE0 Event Block registers. 1.5.1 GPIO Interface Eight GPIO pins are provided for general usage in the system. GPIO[3:0] are dedicated pins and can be configured as inputs or outputs. GPIO[7:4] can be configured as the upper addresses of the ISA bus, SA[23:20]. All GPIOs can also be configured to generate an SMI on input edge transitions.
External Source
XpressAUDIO in the CS5530A offers a combined hardware/software support solution to meet industry standard audio requirements. XpressAUDIO uses VSA technology along with additional hardware features to provide the necessary support for industry standard 16-bit stereo synthesis and OPL3 emulation. The hardware portion of the XpressAUDIO subsystem can broadly be divided into two categories. Hardware for: * Transporting streaming audio data to/from the system memory and an AC97 codec. * VSA technology support. 1.6.1 AC97 Codec Interface The CS5530A provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec which supports an independent input and output sample rate conversion interface (e.g., National Semiconductor LM4548) can be used with the CS5530A. This type of codec allows for a design which meets the requirements for PC97 and PC98-compliant audio as defined by Microsoft Corporation. Figure 1-2 shows the codec and CS5530A signal connections. For specifics on the serial interface, refer to the appropriate codec manufacturer's data sheet. Low latency audio I/O is accomplished by a buffered PCI bus mastering controller.
BITCLK
BIT_CLK 24.576 MHz SYNC PC_BEEP SDATA_IN SDATA_OUT
GeodeTM CS5530A SYNC
PC_BEEP SDAT_I SDAT_O
AC97 Codec
Figure 1-2. AC97 Codec Signal Connections
1.6.2 VSA Technology Support Hardware The CS5530A I/O companion incorporates the required hardware in order to support VSA technology for the capture and playback of audio using an external codec. This eliminates much of the hardware traditionally associated with industry standard audio functions. XpressAUDIO software provides 16-bit compatible sound. This software is available to OEMs for incorporation into the system BIOS ROM.
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Architecture Overview (Continued)
1.7 DISPLAY SUBSYSTEM EXTENSIONS
* Gamma RAM -- Brightness and contrast control * Display Interface -- Integrated RGB Video DACs -- VESA DDC2B/DPMS support -- Flat panel interface Figure 1-3 shows the data path of the display subsystem extensions. The CS5530A incorporates extensions to the GX-series processor's display subsystem. These include: * Video Accelerator -- Buffers and formats input YUV video data from the processor -- 8-bit interface to the processor -- X & Y scaler with bilinear filter -- Color space converter (YUV to RGB) * Video Overlay Logic -- Color key -- Data switch for graphics and video data
Input Formatter
Buffer 0
24
Buffer 1 VID_DATA[7:0]
8
Formatter / Scaler
Vertical Filter
Horizontal Filter
Color Space Converter
Buffer 2
(3x360x32 bit) 24
Video
Color Key Register
24 24
Color Compare
24
Enable Gamma Correction Register
24
PIXEL[23:0]
Bypass
24 8 each
Dither
18
FP_DATA RGB to CRT
24
Gamma RAM
DAC
Figure 1-3. 8-Bit Display Subsystem Extensions
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Architecture Overview (Continued)
1.8 CLOCK GENERATION 1.9 UNIVERSAL SERIAL BUS
In a CS5530A/GX-series processor based system, the CS5530A generates only the video DOT clock (DCLK) for the CPU and the ISA clock. All other clocks are generated by an external clock chip. The ISACLK is created by dividing the PCICLK. For ISA compatibility, the ISACLK nominally runs at 8.33 MHz or less. The ISACLK dividers are programmed via F0 Index 50h[2:0]. DCLK is generated from the 14.31818 MHz input (CLK_14MHZ). A combination of a phase locked loop (PLL), linear feedback shift register (LFSR) and divisors are used to generate the desired frequencies for the DCLK. The divisors and LFSR are configurable through the F4BAR+Memory Offset 24h. For applications that do not use the GX-series processor's graphics subsystem, this is an available clock for general purpose use. Figure 1-4 shows a block diagram for clock generation within the CS5530A. The CS5530A provides two complete, independent USB ports. Each port has a Data "-" and a Data "+" pin. The USB controller is a compliant Open Host Controller Interface (OpenHCI). The OpenHCI specification provides a register-level description for a host controller, as well as a common industry hardware/software interface and drivers (see OpenHCI Specification, Revision 1.0, for description).
TVCLK
M U X DCLK PLL
DCLK
CLK_14MHZ
PCICLK
/N
ISACLK
Figure 1-4. CS5530A Clock Generation
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Architecture Overview (Continued)
1.10 PROCESSOR SUPPORT
The traditional south bridge functionality included in the CS5530A I/O companion chip has been designed to support the GX-series of processors. When combined with a GX-series processor, the CS5530A provides a bridge which supports a standard ISA bus and system ROM. As part of the video subsystem, the CS5530A provides MPEG video acceleration and a digital RGB interface, to allow direct connection to TFT LCD panels. This chip also integrates a gamma RAM and three DACs, allowing for direct connection of a CRT monitor. Figure 1-5 shows a typical system block diagram. For detailed information regarding processor signal connections refer to Section 3.1 "Processor Interface" on page 42.
Memory Data Bus Memory
Memory Port
YUV Port (Video)
Clocks
GeodeTM GX-Series Processor
Serial Packet RGB Port (Graphics)
USB (2 Ports)
CRT
PCI Interface
PCI Bus Speakers Graphics Data Video Data CD ROM Audio AC97 Codec GeodeTM CS5530A I/O Companion Analog RGB Digital RGB Ultra DMA/33 IDE Bus Microphone GPIOs DC-DC & Battery SuperI/O ISA Bus BIOS IDE Devices TFT Flat Panel or TV NTSC/PAL Encoder
Figure 1-5. Example System Block Diagram
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2.0
Signal Definitions
pins organized by their functional groupings (internal test and electrical pins are not shown).
This section defines the signals and describes the external interface of the Geode CS5530A. Figure 2-1 shows the
CPU Interface
INTR SMI# IRQ13 PSERIAL SUSP# SUSPA# SUSP_3V HOLD_REQ# AD[31:0] C/BE[3:0]# INTA#-INTD# REQ# GNT# FRAME# IRDY# TRDY# STOP# LOCK# DEVSEL# PAR PERR# SERR# KBROMCS# PC_BEEP SDATA_OUT SDATA_IN SYNC BIT_CLK PCLK PIXEL[23:0] ENA_DISP HSYNC VSYNC HSYNC_OUT VSYNC_OUT DDC_SCL DDC_SDA IREF EXTVREFIN AVDD1-3 AVSS1-5 IOUTR IOUTG IOUTB
USBCLK TVCLK DCLK PCICLK ISACLK CLK14_MHZ CLK_32K PCI_RST# POR# CPU_RST D+_PORT1 D-_PORT1 D+_PORT2 D-_PORT2 POWER_EN OVER_CUR# IDE_ADDR[2:0] IDE_RST# IDE_CS0# IDE_CS1# IDE_DREQ0 IDE_DREQ1 IDE_DACK0# IDE_DACK1# IDE_IORDY0 IDE_IORDY1 IDE_IOW0# IDE_IOW1# IDE_IOR0# IDE_IOR1# IDE_DATA[15:0]
Clocks
Reset
USB
PCI Bus
GeodeTM CS5530A I/O Companion
Note: Pins that change function when ISA Master mode is invoked are represented with the ISA Master Mode function signal name in parenthesis.
ROM Interface
IDE Controller
Audio Interface
Display: Pixel Port
Display: CRT
Analog
Display: TFT/TV
FP_DATA17 (MASTER#) FP_DATA16 (SA_OE#) FP_DATA[15:0] (SA[15:0]) FP_CLK (No Function) FP_CLK_EVEN (No Function) FP_HSYNC_OUT (SMEMW#) FP_VSYNC_OUT (SMEMR#) FP_DISP_ENA_OUT (No Function) FP_ENA_VDD (No Function) FP_ENA_BKL (No Function) FP_HSYNC (No Function) FP_VSYNC (No Function) VID_DATA[7:0] VID_RDY VID_CLK VID_VAL
SA[19:16] (SD[15:0]) SA[15:0]/SD[15:0] (SA_DIR) SA_LATCH SBHE# BALE IOCHRDY ZEROWS# IOCS16# IOR# IOW# MEMCS16# MEMR# MEMW# AEN IRQ[15:14], [12:9], [7:3], 1 IRQ8# DRQ[7:5], [3:0] DACK#[7:5], [3:0] TC SMEMW#/RTCCS# SMEMR#/RTCALE PLLDVD PLLVAA PLLAGD PLLDGN
ISA Bus
External RTC
Analog
DCLKPLL
Display: MPEG
GPCS# GPORT_CS# (SA[23:20]) GPIO[7:4]/SA[23:20] GPIO[3:2] GPIO1/SDATA_IN2 GPIO0
Game Port/ GPIO
Figure 2-1. CS5530A Signal Groups
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GeodeTM CS5530A
Signal Definitions (Continued)
2.1 PIN ASSIGNMENTS
The tables in this section use several common abbreviations. Table 2-1 lists the mnemonics and their meanings. Figure 2-2 shows the pin assignment for the CS5530A with Tables 2-2 and 2-3 listing the pin assignments sorted by pin number and alphabetically by signal name, respectively. In Section 2.2 "Signal Descriptions" on page 23 a description of each signal within its associated functional group is provided. In the signal definitions, references to F0-F4, F1BAR, F2BAR, F3BAR, F4BAR, and PCIUSB are made. These terms relate to designated register spaces. Refer to Table 4-1 "PCI Configuration Address Register (0CF8h)" on page 141 for details regarding these register spaces and their access mechanisms. I I/O O OD
Table 2-1. Pin Type Definitions
Mnemonic Definition Input pin1 Bidirectional pin1,2 Output pin1, 2 Open-drain output structure that allows multiple devices to share the pin in a wired-OR configuration Pull-up resistor Schmitt Trigger Power pin Ground pin The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at a high voltage level. All buffers are 5 volt tolerant. All digital bidirectional and output pins can be TRISTATE signals unless a weak pull-up is enabled.
PU SMT VDD (PWR) VSS (GND) #
1. 2.
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Signal Definitions (Continued)
1 A
PIX0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 A
PIX1
PIX2 PIX4
PIX7 PIX5
PIX10 VSYNC
VCLK PIX8
PIX12 VDVAL
PIX16 PIX15
PIX19
DCLK
VDAT0 VDAT5
PCLK
INTA# INTD#
AD0 AD3
AD7 AD5
AD9 AD6
AD12
AD10
AD15
PAR
SERR# DVSL# C/BE2# AD17 AD18
AD16
B
ENADISP TVCLK PIX18 VDRDY PIX22 VDAT6 VDAT2 C/BE0# AD11 AD14 C/BE1# PERR# TRDY# IRDY# AD19
B C
FPVSY FPHSY VDD TEST PIX3 PIX11 HSYN PIX14 PIX17 PIX21 PIX23 VDAT3 VDAT7 VDAT1 PRST# INTC# AD2 AD4 VSS AD8 VDD VSS AD13 VSS VDD LOCK# FRAM# VDD GNT# AD20 VDD AD25 AD21 AD22
C D
FPD11 NC VSS VSS VDD FPD6 PIX6 PIX9 PIX13 VSS PIX20 VDD VDAT4 VSS VSS AD1 INTB# VSS VDD VSS VSS VSS VSS VSS VSS AD26 C/BE3#
D E
FPHSYO FPD10 FPVSYO AD23 AD24 STOP#
E F
FPD9 FPDISENO FPD17 AD27
F G
FPD8 FPD5 FPD7 AD28 AD29
G H
FPD4 FPD15 FPD16 FPD1 VSS
Index Mark
VSS VSS VDD AD30 AD31 HDRQ#
H J
J
FPD3 FPD2 FPENBKL REQ# PCICLK
CS5530A
K
FPD14 FPD13 FPD0 VSS
K
VSS VDD PLDVD POR# CPURST SUSP#
GeodeTM
L
FPD12 FPEVDD FPCKEV VDD
L
SUSP3V SUSPA# PSERL
M
FPCLK DDCSCL VSS DDCSDA VSS AVDD3
M
VSS NC PLVAA NC
N
HSYNO VSYNO
N
PLLTEST PLAGD PLDGN
P
AVSS4 AVSS5 IOUTR IOUTG AVSS1 IREF AVSS2 AVSS3 SDATI
P
VSS 14MHZ SMI# INTR
R
IOUTB
R
IRQ13 DIOW0# DIOR1# DIOR0#
T
NC XVREFI AVDD2
T
VDD DDCK1# DIOW1# DDCK0#
U
AVDD1 VDD_USB SYNC
U
IDED7 VSS VSS VDD IDED6 IDEA0 IDEA1
V
SDATO BITCLK PCBEEP PWREN
V
IDED8 IDED10 DCS0#
W
USBCLK NC OVRCUR# VSS NC VSS IDEA2 DRST# IDED5
W Y
D-PT1 D+PT1 IDED11 IDED9 DCS1#
Y AA
D-PT2 D+PT2 NC AVSS_USB NC AVDD_USB NC VSS VSS SA3 DCK7# DCK1# VSS SA2 SA0 VDD SA19 DRQ2 IOW# VSS DRQ1 IOR# VSS DRQ3 IRQ5 IRQ1 IRQ3 MCS16# VSS VDD IRQ14 VSS DRQ5 VDD SA9 SA10 GPIO5 GPIO0
(Top View: Marking orientation is as shown)
VSS IDED1 IDED12 IDED4 NC NC NC IDED15 IDED2 IDED13 IDED3
AA AB AC
AB AC
NC VSS VDD DREQ1 IDED14 IDED0
AD
NC NC NC NC SMEMR# SA5 ISACLK DCK6# DCK0# SA1 SA4 DCK5# AEN SA16 SA18 IRQ7 IRQ8# IRQ6 SLTCH IRQ4 TC IRQ15 VSS GPTCS# GPIO4 SA12 SA13 DRQ7 SA14 IORDY0 DREQ0
AD AE
NC 32K KRMCS# IRQ9 SA6 IRQ10 SBHE# DRQ0 MEMR# DRQ6 CS16# IRQ12 IRQ11 SA8 GPIO6 GPIO1 SA15 IORDY1
AE AF
NC NC SMEMW# SA7 DCK3# DCK2# BALE 0WS# CHRDY SA17 MEMW# SA11 GPIO7 GPIO3 GPIO2 GPCS#
AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Note: Signal names have been abbreviated in this figure due to space constraints. = Multiplexed signal = GND terminal = PWR terminal = Changes function in ISA Master Mode
Figure 2-2. 352 PBGA Pin Assignment Diagram Order Number: CS5530A-UCE
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GeodeTM CS5530A
Signal Definitions (Continued)
Table 2-2. 352 PBGA Pin Assignments - Sorted by Pin Number
Signal Name Pin No. Limited ISA Mode ISA Master Mode Pin No. B26 AD19 C1 FP_VSYNC C2 FP_HSYNC C3 VDD C4 PIXEL3 C5 PIXEL11 C6 HSYNC C7 PIXEL14 C8 PIXEL17 C9 PIXEL21 C10 PIXEL23 C11 VID_DATA3 C12 VID_DATA7 C13 VID_DATA1 C14 PCI_RST# C15 INTC# C16 AD2 C17 AD4 C18 VSS C19 VDD C20 AD13 C21 VSS C22 LOCK# C23 FRAME# C24 VDD C25 AD21 C26 AD22 D1 FP_DATA11 D2 NC D3 TEST D4 VSS D5 PIXEL6 D6 PIXEL9 D7 PIXEL13 D8 VSS D9 PIXEL20 D10 VDD D11 VID_DATA4 D12 VSS D13 VSS D14 AD1 D15 INTB# D16 VSS D17 VDD D18 AD8 D19 VSS D20 VSS D21 VDD D22 VSS D23 VSS D24 GNT# SA11 No Function No Function Signal Name Limited ISA Mode ISA Master Mode Pin No. D25 AD26 D26 C/BE3# E1 FP_HSYNC_OUT E2 FP_DATA10 E3 FP_VSYNC_OUT E4 VSS E23 VSS E24 AD20 E25 AD23 E26 STOP# F1 FP_DATA9 SA9 SMEMW# SA10 SMEMR# Signal Name Limited ISA Mode ISA Master Mode
A1 PIXEL0 A2 PIXEL1 A3 PIXEL2 A4 PIXEL7 A5 PIXEL10 A6 VID_CLK A7 PIXEL12 A8 PIXEL16 A9 PIXEL19 A10 DCLK A11 VID_DATA0 A12 VID_DATA5 A13 PCLK A14 INTA# A15 AD0 A16 AD7 A17 AD9 A18 AD12 A19 AD10 A20 AD15 A21 PAR A22 SERR# A23 DEVSEL# A24 C/BE2# A25 AD17 A26 AD16 B1 ENA_DISP B2 TVCLK B3 PIXEL4 B4 PIXEL5 B5 VSYNC B6 PIXEL8 B7 VID_VAL B8 PIXEL15 B9 PIXEL18 B10 VID_RDY B11 PIXEL22 B12 VID_DATA6 B13 VID_DATA2 B14 INTD# B15 AD3 B16 AD5 B17 AD6 B18 C/BE0# B19 AD11 B20 AD14 B21 C/BE1# B22 PERR# B23 TRDY# B24 IRDY# B25 AD18
F2 FP_DISP_ENA_OUT No Function F3 FP_DATA17 F4 VDD F23 VSS F24 VDD F25 AD24 F26 AD27 G1 FP_DATA8 G2 FP_DATA5 G3 FP_DATA7 G4 FP_DATA6 G23 VSS G24 AD25 G25 AD28 G26 AD29 H1 FP_DATA4 H2 FP_DATA15 H3 FP_DATA16 H4 VSS H23 VSS H24 VDD H25 AD31 H26 HOLD_REQ# J1 FP_DATA3 J2 FP_DATA1 J3 FP_DATA2 J4 FP_ENA_BKL J23 VSS J24 AD30 J25 REQ# J26 PCICLK K1 FP_DATA14 K2 FP_DATA13 K3 FP_DATA0 K4 VSS K23 VSS K24 POR# K25 CPU_RST K26 SUSP# L1 FP_DATA12 SA12 SA14 SA13 SA0 SA3 SA1 SA2 No Function SA4 SA15 SA_OE# SA8 SA5 SA7 SA6 MASTER#
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Signal Definitions (Continued)
Table 2-2.
Signal Name Pin No. Limited ISA Mode ISA Master Mode No Function No Function Pin No.
352 PBGA Pin Assignments - Sorted by Pin Number (Continued)
Signal Name Limited ISA Mode ISA Master Mode Pin No. Signal Name Limited ISA Mode ISA Master Mode
L2 FP_ENA_VDD L3 FP_CLK_EVEN L4 VDD L23 VDD L24 SUSP_3V L25 SUSPA# L26 PSERIAL M1 FP_CLK M2 DDC_SCL M3 VSS M4 DDC_SDA M23 PLLDVD M24 VSS M25 PLLVAA M26 NC N1 HSYNC_OUT N2 VSYNC_OUT N3 VSS N4 AVDD3 (DAC) N23 PLLTEST N24 NC N25 PLLAGD N26 PLLDGN P1 AVSS4 (ICAP) P2 AVSS5 (DAC) P3 IOUTR P4 IOUTG P23 VSS P24 CLK_14MHZ P25 SMI# P26 INTR R1 IOUTB R2 AVSS1 (DAC) R3 IREF R4 AVSS2 (ICAP) R23 IRQ13 R24 IDE_IOW0# R25 IDE_IOR1# R26 IDE_IOR0# T1 NC T2 EXTVREFIN T3 AVDD2 (VREF) T4 AVSS3 (VREF) T23 VDD T24 IDE_DACK1# T25 IDE_IOW1# T26 IDE_DACK0# U1 AVDD1 (DAC) U2 VDD_USB U3 SYNC U4 SDATA_IN
U23 IDE_DATA7 U24 IDE_DATA6 U25 IDE_ADDR0 U26 IDE_ADDR1 V1 SDATA_OUT V2 BIT_CLK V3 PC_BEEP
AC8 DACK1# AC9 VSS AC10 VDD AC11 IOW# AC12 VSS AC13 VSS AC14 IRQ3 AC15 MEMCS16# AC16 VSS AC17 IRQ14 AC18 VSS AC19 VDD AC20 SA10/SD10 AC21 GPIO5/SA21 AC22 GPIO0 AC23 VSS AC24 IDE_DREQ1 AC25 IDE_DATA14 AC26 IDE_DATA0 AD1 NC AD2 NC AD3 NC AD4 SMEMR#/RTCALE AD5 SA5/SD5 AD6 ISACLK AD7 DACK6# AD8 DACK0# AD9 SA2/SD2 AD10 SA19 AD11 SA16 AD12 DRQ1 AD13 DRQ3 AD14 IRQ7 AD15 SA_LATCH AD16 VDD AD17 IRQ15 AD18 DRQ5 AD19 SA9/SD9 AD20 VSS AD21 GPORT_CS# AD22 GPIO4/SA20 AD23 VDD AD24 SA14/SD14 AD25 IDE_IORDY0 AD26 IDE_DREQ0 AE1 NC AE2 NC AE3 CLK_32K AE4 KBROMCS# SD3 AE5 IRQ9 AE6 SA1/SD1 SD1 SD14 SA20 SD9 SA_DIR SD2 SD5 SD10 SA21
No Function
V4 POWER_EN V23 VSS V24 IDE_DATA8 V25 IDE_DATA10 V26 IDE_CS0# W1 USBCLK W2 NC W3 OVER_CUR# W4 VSS W23 VSS W24 IDE_ADDR2 W25 IDE_RST# W26 IDE_DATA5 Y1 D-_PORT1 Y2 D+_PORT1 Y3 NC Y4 VSS Y23 VDD Y24 IDE_DATA11 Y25 IDE_DATA9 Y26 IDE_CS1# AA1 D-_PORT2 AA2 D+_PORT2 AA3 NC AA4 AVSS_USB AA23 VSS AA24 IDE_DATA1 AA25 IDE_DATA12 AA26 IDE_DATA4 AB1 NC AB2 NC AB3 NC AB4 AVDD_USB AB23 IDE_DATA15 AB24 IDE_DATA2 AB25 IDE_DATA13 AB26 IDE_DATA3 AC1 NC AC2 NC AC3 NC AC4 VSS AC5 VSS AC6 SA3/SD3 AC7 DACK7#
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GeodeTM CS5530A
Signal Definitions (Continued)
Table 2-2.
Signal Name Pin No. Limited ISA Mode ISA Master Mode Pin No.
352 PBGA Pin Assignments - Sorted by Pin Number (Continued)
Signal Name Limited ISA Mode ISA Master Mode SD22 Pin No. AF13 IRQ1 AF14 IRQ6 SD15 AF15 TC AF16 IOCS16# AF17 IRQ12 AF18 IRQ11 AF19 SA8/SD8 SD7 SD6 SD4 AF20 MEMW# AF21 SA11/SD11 AF22 DRQ7 AF23 GPIO7/SA23 AF24 GPIO3 AF25 GPIO2 AF26 GPCS# SA23 SD11 SD8 Signal Name Limited ISA Mode ISA Master Mode
AE7 DACK5# AE8 AEN AE9 SA0/SD0 AE10 DRQ2 AE11 SA18 AE12 IOR# AE13 IRQ5 AE14 IRQ8# AE15 IRQ4 AE16 IRQ10 AE17 SBHE# AE18 DRQ0 AE19 MEMR# AE20 DRQ6 AE21 SA12/SD12 AE22 SA13/SD13 SD12 SD13 SD0
AE23 GPIO6/SA22 AE24 GPIO1/SDATA_IN2 AE25 SA15/SD15 AE26 IDE_IORDY1 AF1 NC AF2 NC AF3 SMEMW#/RTCCS# AF4 SA7/SD7 AF5 SA6/SD6 AF6 SA4/SD4 AF7 DACK3# AF8 DACK2# AF9 BALE AF10 ZEROWS# AF11 IOCHRDY AF12 SA17
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Signal Definitions (Continued)
Table 2-3. 352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name Limited ISA Mode AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AEN AVDD1 (DAC) AVDD2 (VREF) AVDD3 (DAC) AVDD_USB AVSS1 (DAC) AVSS2 (ICAP) AVSS3 (VREF) AVSS4 (ICAP) AVSS5 (DAC) AVSS_USB BALE BIT_CLK C/BE0# C/BE1# C/BE2# C/BE3# CLK_14MHZ CLK_32K CPU_RST ISA Master Mode Pin Type1 Buffer Type2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I, Analog I, Analog I, Analog PWR I, Analog I, Analog I, Analog I, Analog I, Analog GND O I I/O I/O I/O I/O I (SMT) I/O O PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI 8 mA ----------8 mA 8 mA PCI PCI PCI PCI CLK 8 mA 8 mA Pin No. A15 D14 C16 B15 C17 B16 B17 A16 D18 A17 A19 B19 A18 C20 B20 A20 A26 A25 B25 B26 E24 C25 C26 E25 F25 G24 D25 F26 G25 G26 J24 H25 AE8 U1 T3 N4 AB4 R2 R4 T4 P1 P2 AA4 AF9 V2 B18 B21 A24 D26 P24 AE3 K25 Signal Name Limited ISA Mode DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7# DCLK DDC_SCL DDC_SDA DEVSEL# D-_PORT1 D+_PORT1 D-_PORT2 D+_PORT2 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 ENA_DISP EXTVREFIN FP_CLK FP_CLK_EVEN FP_DATA0 FP_DATA1 FP_DATA2 FP_DATA3 FP_DATA4 FP_DATA5 FP_DATA6 FP_DATA7 FP_DATA8 FP_DATA9 FP_DATA10 FP_DATA11 FP_DATA12 FP_DATA13 FP_DATA14 FP_DATA15 FP_DATA16 FP_DATA17 FP_DISP_ENA_OUT FP_ENA_BKL FP_ENA_VDD FP_HSYNC FP_HSYNC_OUT FP_VSYNC FP_VSYNC_OUT FRAME# No Function No Function SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA_OE# MASTER# No Function No Function No Function No Function SMEMW# No Function SMEMR# ISA Master Mode Pin Type1 Buffer Type2 O O O O O O O O O I/O I/O I/O I/O I/O I/O I I I I I I I I I, Analog O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O O O I O I O I/O 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA DOTCLK 8 mA 8 mA PCI USB USB USB USB 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA -FP_CLK 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA PCI Pin No. AD8 AC8 AF8 AF7 AE7 AD7 AC7 A10 M2 M4 A23 Y1 Y2 AA1 AA2 AE18 AD12 AE10 AD13 AD18 AE20 AF22 B1 T2 M1 L3 K3 J2 J3 J1 H1 G2 G4 G3 G1 F1 E2 D1 L1 K2 K1 H2 H3 F3 F2 J4 L2 C2 E1 C1 E3 C23
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GeodeTM CS5530A
Signal Definitions (Continued)
Table 2-3.
Signal Name Limited ISA Mode GNT# GPCS# GPIO0 GPIO1/SDATA_IN2 GPIO2 GPIO3 GPIO4/SA20 GPIO5/SA21 GPIO6/SA22 GPIO7/SA23 GPORT_CS# HOLD_REQ# (strap pin) HSYNC HSYNC_OUT IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_DREQ0 IDE_DREQ1 IDE_IOR0# IDE_IOR1# IDE_IORDY0 IDE_IORDY1 IDE_IOW0# IDE_IOW1# IDE_RST# INTA# INTB# INTC# INTD# INTR (strap pin) SA20 SA21 SA22 SA23 ISA Master Mode Pin Type1 Buffer Type2 I O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O O I I O O O I I I I I/O PCI 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA PCI 8 mA 8 mA IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE PCI PCI PCI PCI 8 mA Pin No. D24 AF26 AC22 AE24 AF25 AF24 AD22 AC21 AE23 AF23 AD21 H26 C6 N1 U25 U26 W24 V26 Y26 T26 T24 AC26 AA24 AB24 AB26 AA26 W26 U24 U23 V24 Y25 V25 Y24 AA25 AB25 AC25 AB23 AD26 AC24 R26 R25 AD25 AE26 R24 T25 W25 A14 D15 C15 B14 P26
352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name Limited ISA Mode IOCHRDY IOCS16# IOR# IOUTB IOUTR IOUTG IOW# IRDY# IREF IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8# IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 ISACLK KBROMCS# LOCK# MEMCS16# MEMR# MEMW# NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC OVER_CUR# PAR ISA Master Mode Pin Type1 Buffer Type2 I/O, OD I I/O (PU) O, Analog O, Analog O, Analog I/O (PU) I/O I, Analog I I I I I I I I I I I I I I O O I/O I/O, OD I/O (PU) I/O (PU) --------------------I I/O 8 mA 8 mA 8 mA ---8 mA PCI -8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA PCI 8 mA 8 mA 8 mA --------------------8 mA PCI Pin No. AF11 AF16 AE12 R1 P3 P4 AC11 B24 R3 AF13 AC14 AE15 AE13 AF14 AD14 AE14 AE5 AE16 AF18 AF17 R23 AC17 AD17 AD6 AE4 C22 AC15 AE19 AF20 AA3 AB1 AB2 AB3 AC1 AC2 AC3 AD1 AD2 AD3 AE1 AE2 AF1 AF2 D2 M26 N24 T1 W2 Y3 W3 A21
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Signal Definitions (Continued)
Table 2-3.
Signal Name Limited ISA Mode PC_BEEP PCICLK PCI_RST# PCLK PERR# PIXEL0 PIXEL1 PIXEL2 PIXEL3 PIXEL4 PIXEL5 PIXEL6 PIXEL7 PIXEL8 PIXEL9 PIXEL10 PIXEL11 PIXEL12 PIXEL13 PIXEL14 PIXEL15 PIXEL16 PIXEL17 PIXEL18 PIXEL19 PIXEL20 PIXEL21 PIXEL22 PIXEL23 PLLAGD PLLDGN PLLDVD PLLTEST PLLVAA POR# POWER_EN PSERIAL REQ# SA0/SD0 SA1/SD1 SA2/SD2 SA3/SD3 SA4/SD4 SA5/SD5 SA6/SD6 SA7/SD7 SA8/SD8 SA9/SD9 SA10/SD10 SA11/SD11 SA12/SD12 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 ISA Master Mode Pin Type1 Buffer Type2 O I (SMT) O I I/O I I I I I I I I I I I I I I I I I I I I I I I I I, Analog I, Analog I, Analog -I, Analog I O I O I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) 8 mA CLK 8 mA 8 mA PCI 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA -----8 mA 8 mA 8 mA PCI 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Pin No. V3 J26 C14 A13 B22 A1 A2 A3 C4 B3 B4 D5 A4 B6 D6 A5 C5 A7 D7 C7 B8 A8 C8 B9 A9 D9 C9 B11 C10 N25 N26 M23 N23 M25 K24 V4 L26 J25 AE9 AE6 AD9 AC6 AF6 AD5 AF5 AF4 AF19 AD19 AC20 AF21 AE21
352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name Limited ISA Mode SA13/SD13 SA14/SD14 SA15/SD15 SA16 SA17 SA18 SA19 SA_LATCH SBHE# SDATA_IN SDATA_OUT SERR# SMEMR#/RTCALE SMEMW#/RTCCS# SMI# STOP# SUSP# SUSPA# SUSP_3V SYNC TC TEST TRDY# TVCLK USBCLK VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_USB VID_CLK VID_DATA0 VID_DATA1 VID_DATA2 VID_DATA3 VID_DATA4 VID_DATA5 VID_DATA6 SA_DIR ISA Master Mode SD13 SD14 SD15 Pin Type1 Buffer Type2 I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) I/O (PU) O I/O (PU) I O I/O, OD O O I/O I/O O I I/O O O I I/O I I (SMT) PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR I I I I I I I I 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA PCI 8 mA 8 mA 8 mA PCI 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA PCI 8 mA CLK ------------------8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Pin No. AE22 AD24 AE25 AD11 AF12 AE11 AD10 AD15 AE17 U4 V1 A22 AD4 AF3 P25 E26 K26 L25 L24 U3 AF15 D3 B23 B2 W1 D10 D17 AC10 AC19 AD16 AD23 C19 C24 C3 D21 F24 F4 H24 L23 L4 T23 Y23 U2 A6 A11 C13 B13 C11 D11 A12 B12
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GeodeTM CS5530A
Signal Definitions (Continued)
Table 2-3.
Signal Name Limited ISA Mode VID_DATA7 VID_RDY VID_VAL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ISA Master Mode Pin Type1 Buffer Type2 I O I GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 8 mA 8 mA 8 mA -----------------------Pin No. C12 B10 B7 D12 D13 D16 AA23 AC12 AC13 AC16 AC18 AC23 AC4 AC5 AC9 AD20 C18 C21 D19 D20 D22 D23 D4 D8 E23 E4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSYNC VSYNC_OUT ZEROWS#
352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name Limited ISA Mode ISA Master Mode Pin Type1 Buffer Type2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I O I ---------------8 mA 8 mA 8 mA Pin No. F23 G23 H23 H4 J23 K23 K4 M24 M3 N3 P23 V23 W23 W4 Y4 B5 N2 AF10
1. 2.
See Table 2-1 "Pin Type Definitions" on page 14 for pin type definitions. See Table 5-4 "DC Characteristics" on page 238 and Table 58 "AC Characteristics" on page 242 for more information on buffer types. Note that some bidirectional buffers are used as input only, indicated by an "I" in the Pin Type column.
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Signal Definitions (Continued)
2.2
2.2.1
SIGNAL DESCRIPTIONS
Reset Interface Pin No. C14 Pin Type O Description PCI Reset PCI_RST# resets the PCI bus and is asserted while POR# is asserted, and for approximately 9 ms following the deassertion of POR#.
Signal Name PCI_RST#
POR#
K24
I
Power On Reset POR# is the system reset signal generated from the power supply to indicate that the system should be reset.
CPU_RST
K25
O
CPU Reset CPU_RST resets the CPU and is asserted while POR# is asserted, and for approximately 9 ms following the deassertion of POR#. CLK_14MHZ is used to generate this signal.
2.2.2
Clock Interface Pin No. J26 Pin Type I (SMT) I Description PCI Clock The PCI clock is used to drive most circuitry of the CS5530A. Television Clock The TVCLK is an input from a digital NTSC/PAL converter which is optionally re-driven back out onto the DCLK signal under software program control. This is only used if interfacing to a compatible digital NTSC/PAL encoder device.
Signal Name PCICLK
TVCLK
B2
DCLK
A10
O
DOT Clock DOT clock is generated by the CS5530A and typically connects to the processor to create the clock used by the graphics subsystem. The minimum frequency of DCLK is 10 MHz and the maximum is 200 MHz. However, when DCLK is used as the graphics subsystem clock, the Geode processor determines the maximum DCLK frequency.
ISACLK
AD6
O
ISA Bus Clock ISACLK is derived from PCICLK and is typically programmed for approximately 8 MHz. F0 Index 50h[2:0] are used to program the ISA clock divisor.
CLK_14MHZ
P24
I (SMT)
14.31818 MHz Clock This clock is used to generate CPU_RST to the Geode processor. DOT clock (DCLK) is also derived from this clock. USBCLK This input is used as the clock source for the USB. In this mode, a 48 MHz clock source input is required. 32 KHz Clock CLK_32K is a 32.768 KHz clock used to generate reset signals, as well as to maintain power management functionality. It should be active when power is applied to the CS5530A. CLK_32K can be an input or an output. As an output CLK_32K is internally derived from CLK_14MHZ. F0 Index 44h[5:4] are used to program this pin.
USBCLK
W1
I (SMT)
CLK_32K
AE3
I/O
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Signal Definitions (Continued)
2.2.3 CPU Interface Pin No. P26 Strap Option Pin Pin Type O Description CPU Interrupt Request INTR is the level output from the integrated 8259 PICs and is asserted if an unmasked interrupt request (IRQn) is sampled active. I Strap Option Select Pin Pin P26 is a strap option select pin. It is used to select whether the CS5530A operates in Limited ISA or ISA Master mode. ISA Limited Mode--Strap pin P26 low through a 10-kohm resistor. ISA Master Mode--Strap pin P26 high through a 10-kohm resistor. SMI# P25 I/O System Management Interrupt SMI# is a level-sensitive interrupt to the CPU that can be configured to assert on a number of different system events. After an SMI# assertion, System Management Mode (SMM) is entered, and program execution begins at the base of SMM address space. Once asserted, SMI# remains active until all SMI sources are cleared. IRQ13 R23 I IRQ13 IRQ13 is an input from the processor indicating that a floating point error was detected and that INTR should be asserted. PSERIAL L26 I Power Management Serial Interface PSERIAL is the unidirectional serial data link between the GX-series processor and the CS5530A. An 8-bit serial data packet carries status on power management events within the CPU. Data is clocked synchronous to the PCICLK input clock. SUSP# K26 O CPU Suspend SUSP# asserted requests that the CPU enters Suspend mode and the CPU asserts SUSPA# after completion. The SUSP# pin is deasserted if SUSP# has gone active and any Speedup or Resume event has occurred, including expiration of the Suspend Modulation ON timer, which is loaded from F0 Index 95h. If the SUSP#/SUSPA# handshake is configured as a system 3 Volt Suspend, the deassertion of SUSP# is delayed by an interval programmed in F0 Index BCh[7:4] to allow the system clock chip and the processor to stabilize. The SUSP#/SUSPA# handshake occurs as a result of a write to the Suspend Notebook Command Register (F0 Index AFh), or expiration of the Suspend Modulation OFF timer (loaded from F0 Index 94h) when Suspend Modulation is enabled. Suspend Modulation is enabled via F0 Index 96h[0]. If SUSPA# is asserted as a result of a HALT instruction, SUSP# does not deassert when the Suspend Modulation ON timer (loaded from F0 Index 95h) expires. SUSPA# L25 I CPU Suspend Acknowledge SUSPA# is a level input from the processor. When asserted it indicates the CPU is in Suspend mode as a result of SUSP# assertion or execution of a HALT instruction.
Signal Name INTR
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GeodeTM CS5530A
Signal Definitions (Continued)
2.2.3 CPU Interface (Continued) Pin No. L24 Pin Type I/O Description Suspend 3 Volt Active SUSP_3V can be connected to the output enable (OE) of a clock synthesis or buffer chip to stop the clocks to the system. SUSP_3V is asserted after the SUSP#/SUSPA# handshake that follows a write to the Suspend Notebook Command Register (F0 Index AFh) with bit 0 set in the Clock Stop Control Register (F0 Index BCh). As an input, SUSP_3V is sampled during power-on-reset to determine the inactive state. This allows the system designer to match the active state of SUSP_3V to the inactive state for a clock driver output enabled with a pullup/down 10-kohm resistor. If pulled down, SUSP_3V is active high. If pulled up, SUSP_3V is active low.
Signal Name SUSP_3V
2.2.4
PCI Interface Pin No. Refer to Table 2-3 Pin Type I/O Description PCI Address/Data AD[31:0] is a physical address during the first clock of a PCI transaction; it is the data during subsequent clocks. When the CS5530A is a PCI master, AD[31:0] are outputs during the address and write data phases, and are inputs during the read data phase of a transaction. When the CS5530A is a PCI slave, AD[31:0] are inputs during the address and write data phases, and are outputs during the read data phase of a transaction.
Signal Name AD[31:0]
C/BE[3:0]#
D26, A24, B21, B18
I/O
PCI Bus Command and Byte Enables During the address phase of a PCI transaction, C/BE[3:0]# define the bus command. During the data phase of a transaction, C/BE[3:0]# are the data byte enables. C/BE[3:0]# are outputs when the CS5530A is a PCI master and inputs when it is a PCI slave.
INTA#, INTB#, INTC#, INTD#
A14, D15, C15, B14
I
PCI Interrupt Pins The CS5530A provides inputs for the optional "level-sensitive" PCI interrupts (also known in industry terms as PIRQx#). These interrupts may be mapped to IRQs of the internal 8259s using PCI Interrupt Steering Registers 1 and 2 (F0 Index 5Ch and 5Dh). The USB controller uses INTA# as its output signal. Refer to PCIUSB Index 3Dh.
REQ#
J25
O
PCI Bus Request The CS5530A asserts REQ# in response to a DMA request or ISA master request to gain ownership of the PCI bus. The REQ# and GNT# signals are used to arbitrate for the PCI bus. REQ# should connect to the REQ0# of the GX-series processor and function as the highest-priority PCI master.
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Signal Definitions (Continued)
2.2.4 PCI Interface (Continued) Pin No. D24 Pin Type I Description PCI Bus Grant GNT# is asserted by an arbiter that indicates to the CS5530A that access to the PCI bus has been granted. GNT# should connect to GNT0# of the GX-series processor and function as the highest-priority PCI master. HOLD_REQ# H26 Strap Option Pin O PCI Bus Hold Request This pin's function as HOLD_REQ# is no longer applicable. I Strap Option Select Pin Pin H26 is a strap option select pin. It allows selection of which address bits are used as the IDSEL. Strap pin H26 low: IDSEL = AD28 (Chipset Register Space) and AD29 (USB Register Space) Strap pin H26 high: IDSEL = AD26 (Chipset Register Space) and AD27 (USB Register Space) FRAME# C23 I/O PCI Cycle Frame FRAME# is asserted to indicate the start and duration of a transaction. It is deasserted on the final data phase. FRAME# is an input when the CS5530A is a PCI slave. IRDY# B24 I/O PCI Initiator Ready IRDY# is driven by the master to indicate valid data on a write transaction, or that it is ready to receive data on a read transaction. When the CS5530A is a PCI slave, IRDY# is an input that can delay the beginning of a write transaction or the completion of a read transaction. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. TRDY# B23 I/O PCI Target Ready TRDY# is asserted by a PCI slave to indicate it is ready to complete the current data transfer. TRDY# is an input that indicates a PCI slave has driven valid data on a read or a PCI slave is ready to accept data from the CS5530A on a write. TRDY# is an output that indicates the CS5530A has placed valid data on AD[31:0] during a read or is ready to accept the data from a PCI master on a write. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. STOP# E26 I/O PCI Stop As an input, STOP# indicates that a PCI slave wants to terminate the current transfer. The transfer is either aborted or retried. STOP# is also used to end a burst. As an output, STOP# is asserted with TRDY# to indicate a target disconnect, or without TRDY# to indicate a target retry. The CS5530A asserts STOP# during any cache line crossings if in single transfer DMA mode or if busy.
Signal Name GNT#
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Signal Definitions (Continued)
2.2.4 PCI Interface (Continued) Pin No. C22 Pin Type I/O Description PCI Lock LOCK# indicates an atomic operation that may require multiple transactions to complete. If the CS5530A is currently the target of a LOCKed transaction, any other PCI master request with the CS5530A as the target is forced to retry the transfer. The CS5530A does not generate LOCKed transactions. DEVSEL# A23 I/O PCI Device Select DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and subtractive decoder that it is the target of the current transaction. As an input, DEVSEL# indicates a PCI slave has responded to the current address. As an output, DEVSEL# is asserted one cycle after the assertion of FRAME# and remains asserted to the end of a transaction as the result of a positive decode. DEVSEL# is asserted four cycles after the assertion of FRAME# if DEVSEL# has not been asserted by another PCI device when the CS5530A is programmed to be the subtractive decode agent. The subtractive decode sample point is configured in F0 Index 41h[2:1]. Subtractive decode cycles are passed to the ISA bus. PAR A21 I/O PCI Parity PAR is the parity signal driven to maintain even parity across AD[31:0] and C/BE[3:0]#. The CS5530A drives PAR one clock after the address phase and one clock after each completed data phase of write transactions as a PCI master. It also drives PAR one clock after each completed data phase of read transactions as a PCI slave. PERR# B22 I/O PCI Parity Error PERR# is pulsed by a PCI device to indicate that a parity error was detected. If a parity error was detected, PERR# is asserted by a PCI slave during a write data phase and by a PCI master during a read data phase. When the CS5530A is a PCI master, PERR# is an output during read transfers and an input during write transfers. When the CS5530A is a PCI slave, PERR# is an input during read transfers and an output during write transfers. Parity detection is enabled through F0 Index 04h[6]. An NMI is generated if I/O Port 061h[2] is set. PERR# can assert SERR# if F0 Index 41h[5] is set. SERR# A22 I/O OD PCI System Error SERR# is pulsed by a PCI device to indicate an address parity error, data parity error on a special cycle command, or other fatal system errors. SERR# is an open-drain output reporting an error condition, and an input indicating that the CS5530A should generate an NMI. As an input, SERR# is asserted for a single clock by the slave reporting the error. System error detection is enabled with F0 Index 04h[8]. An NMI is generated if I/O Port 061h[2] is set. PERR# can assert SERR# if F0 Index 41h[5] is set.
Signal Name LOCK#
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Signal Definitions (Continued)
2.2.5 ISA Bus Interface Pin No. AD15 Pin Type O Description Limited ISA Mode: System Address Latch This signal is used to latch the destination address, which is multiplexed on bits [15:0] of the SA/SD bus. ISA Master Mode: System Address Direction Controls the direction of the external 5.0V tolerant transceiver on bits [15:0] of the SA bus. When low, the SA bus is driven out. When high, the SA bus is driven into the CS5530A by the external transceiver. SA_OE#/ FP_DATA16 H3 O Limited ISA Mode: Flat Panel Data Port Line 16 Refer to Section 2.2.11 "Display Interface" on page 35 for this signal's definition. O ISA Master Mode: System Address Transceiver Output Enable Enables the external transceiver on bits [15:0] of the SA bus. MASTER#/ FP_DATA17 F3 O Limited ISA Mode: Flat Panel Data Port Line 17 Refer to Section 2.2.11 "Display Interface" on page 35 for this signal's definition. I ISA Master Mode: Master The MASTER# input asserted indicates an ISA bus master is driving the ISA bus. SA23/GPIO7 SA22/GPIO6 SA21/GPIO5 SA20/GPIO4 AF23 AE23 AC21 AD22 I/O Limited ISA Mode: System Address Bus Lines 23 through 20 or General Purpose I/Os 7 through 4 These pins can function either as the upper four bits of the SA bus or as general purpose I/Os. Programming is done through F0 Index 43h, bits 6 and 2. Refer to Section 2.2.9 "Game Port and General Purpose I/O Interface" on page 33 for further details when used as GPIOs. ISA Master Mode: System Address Bus Lines 23 through 20 The pins function only as the four MSB (most significant bits) of the SA bus. SA[19:16] AD10, AE11, AF12, AD11 Refer to Table 2-3 I/O (PU) System Address Bus Lines 19 through 16 Refer to SA[15:0] signal description.
Signal Name SA_LATCH/ SA_DIR
SA[15:0]/SD[15:0]
I/O (PU)
Limited ISA Mode: System Address Bus / System Data Bus This bus carries both the addresses and data for all ISA cycles. Initially, the address is placed on the bus and then SA_LATCH is asserted in order for external latches to latch the address. At some time later, the data is put on the bus, for a read, or the bus direction is changed to an input, for a write. Pins designated as SA/SD[15:0] are internally connected to a 20-kohm pullup resistor. ISA Master Mode: System Data Bus These pins perform only as SD[15:0] and pins FP_DATA[15:0] take on the functions of SA[15:0]. Pins designated as SA/SD[15:0] are internally connected to a 20-kohm pullup resistor.
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Signal Definitions (Continued)
2.2.5 ISA Bus Interface (Continued) Pin No. E1 Pin Type O Description Limited ISA Mode: Flat Panel Horizontal Sync Output Refer to Section 2.2.11 "Display Interface" on page 35 for this signal's definition. Note that if Limited ISA Mode of operation is selected, SMEMW# is available on pin AF3 (multiplexed with RTCCS#). ISA Master Mode: System Memory Write SMEMW# is asserted for any memory write accesses below 1 MB (i.e., A23:A20 set to 0). This enables 8-bit memory slaves to decode the memory address on SA[19:0]. SMEMR#/ FP_VSYNC_OUT E3 O Limited ISA Mode: Flat Panel Vertical Sync Output Refer to Section 2.2.11 "Display Interface" on page 35 for this signal's definition. Note that if Limited ISA Mode of operation is selected, SMEMR# is available on pin AD4 (multiplexed with RTCALE). ISA Master Mode: System Memory Read SMEMR# is asserted for memory read accesses below 1 MB (i.e., A23:A20 set to 0). This enables 8-bit memory slaves to decode the memory address on SA[19:0]. SMEMW#/ RTCCS# AF3 O System Memory Write / Real-Time Clock Chip Select If Limited ISA Mode of operation has been selected, then SMEMW# can be output on this pin. SMEMW# is asserted for any memory write accesses below 1 MB (i.e., A23:A20 set to 0). This enables 8-bit memory slaves to decode the memory address on SA[19:0]. RTCCS# is a chip select to an external real-time clock chip. This signal is activated on reads or writes to I/O Port 071h. Function selection is made through F0 Index 53h[2]: 0 = SMEMW#, 1 = RTCCS#. SMEMR#/ RTCALE AD4 O System Memory Read / Real-Time Clock Address Latch Enable If Limited ISA Mode of operation has been selected, then SMEMR# can be output on this pin. SMEMR# is asserted for memory read accesses below 1 MB (i.e., A23:A20 set to 0). This enables 8-bit memory slaves to decode the memory address on SA[19:0]. RTCALE is a signal telling an external real-time clock chip to latch the address, which is on the SD bus. Function selection is made through F0 Index 53h[2]: 0 = SMEMR#, 1 = RTCALE. SBHE# AE17 I/O (PU) System Bus High Enable The CS5530A or ISA master asserts SBHE# to indicate that SD[15:8] will be used to transfer a byte at an odd address. SBHE# is an output during non-ISA master DMA operations. It is driven as the inversion of AD0 during 8-bit DMA cycles. It is forced low for all 16-bit DMA cycles. SBHE# is an input during ISA master operations. This pin is internally connected to a 20-kohm pull-up resistor. BALE AF9 O Buffered Address Latch Enable BALE indicates when SA[23:0] and SBHE# are valid and may be latched. For DMA transfers, BALE remains asserted until the transfer is complete.
Signal Name SMEMW#/ FP_HSYNC_OUT
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Signal Definitions (Continued)
2.2.5 ISA Bus Interface (Continued) Pin No. AF11 Pin Type I/O OD Description I/O Channel Ready IOCHRDY deasserted indicates that an ISA slave requires additional wait states. When the CS5530A is an ISA slave, IOCHRDY is an output indicating additional wait states are required. ZEROWS# AF10 I Zero Wait States ZEROWS# asserted indicates that an ISA 8- or 16-bit memory slave can shorten the current cycle. The CS5530A samples this signal in the phase after BALE is asserted. If asserted, it shortens 8-bit cycles to three ISACLKs and 16-bit cycles to two ISACLKs. IOCS16# AF16 I I/O Chip Select 16 IOCS16# is asserted by 16-bit ISA I/O devices based on an asynchronous decode of SA[15:0] to indicate that SD[15:0] will be used to transfer data. 8-bit ISA I/O devices only use SD[7:0]. IOR# AE12 I/O (PU) I/O Read IOR# is asserted to request an ISA I/O slave to drive data onto the data bus. This pin is internally connected to a 20-kohm pull-up resistor. IOW# AC11 I/O (PU) I/O Write IOW# is asserted to request an ISA I/O slave to accept data from the data bus. This pin is internally connected to a 20-kohm pull-up resistor. MEMCS16# AC15 I/O OD Memory Chip Select 16 MEMCS16# is asserted by 16-bit ISA memory devices based on an asynchronous decode of SA[23:17] to indicate that SD[15:0] will be used to transfer data. 8-bit ISA memory devices only use SD[7:0]. MEMR# AE19 I/O (PU) Memory Read MEMR# is asserted for any memory read accesses. It enables 16-bit memory slaves to decode the memory address on SA[23:0]. This pin is internally connected to a 20-kohm pull-up resistor. MEMW# AF20 I/O (PU) Memory Write MEMW# is asserted for any memory write accesses. It enables 16-bit memory slaves to decode the memory address on SA[23:0]. This pin is internally connected to a 20-kohm pull-up resistor. AEN AE8 O Address Enable AEN asserted indicates that a DMA transfer is in progress, informing I/O devices to ignore the I/O cycle. IRQ[15:14], [12:9], [7:3], 1 Refer to Table 2-3 AE14 I ISA Bus Interrupt Request IRQ inputs indicate ISA devices or other devices requesting a CPU interrupt service. I Real-Time Clock Interrupt IRQ8# is the (active-low) interrupt that comes from the external RTC chip and indicates a date/time update has completed.
Signal Name IOCHRDY
IRQ8#
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Signal Definitions (Continued)
2.2.5 ISA Bus Interface (Continued) Pin No. Refer to Table 2-3 Refer to Table 2-3 AF15 Pin Type I Description DMA Request - Channels 7 through 5 and 3 through 0 DRQ inputs are asserted by ISA DMA devices to request a DMA transfer. The request must remain asserted until the corresponding DACK is asserted. O DMA Acknowledge - Channels 7 through 5 and 3 through 0 DACK outputs are asserted to indicate when a DRQ is granted and the start of a DMA cycle. O Terminal Count TC signals the final data transfer of a DMA transfer.
Signal Name DRQ[7:5], DRQ[3:0]
DACK[7:5]#, DACK[3:0]#
TC
2.2.6
ROM Interface Pin No. AE4 Pin Type O Description Keyboard/ROM Chip Select KBROMCS# is the enable pin for the BIOS ROM and for the keyboard controller. For ROM accesses, KBROMCS# is asserted for ISA memory accesses programmed at F0 Index 52h[2:0]. For keyboard controller accesses, KBROMCS# is asserted for I/O accesses to I/O Ports 060h, 062h, 064h, and 066h.
Signal Name KBROMCS#
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Signal Definitions (Continued)
2.2.7 IDE Interface Pin No. W25 Pin Type O Description IDE Reset This signal resets all the devices that are attached to the IDE interface. IDE_ADDR[2:0] W24, U26, U25 Refer to Table 2-3 R26 R25 O IDE Address Bits These address bits are used to access a register or data port in a device on the IDE bus. I/O IDE Data Lines IDE_DATA[15:0] transfers data to/from the IDE devices.
Signal Name IDE_RST#
IDE_DATA[15:0]
IDE_IOR0# IDE_IOR1#
O O
IDE I/O Read for Channels 0 and 1 IDE_IOR0# is the read signal for Channel 0, and IDE_IOR1# is the read signal for Channel 1. Each signal is asserted on read accesses to the corresponding IDE port addresses. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle -- DMARDY0# and DMARDY1# Write Cycle -- STROBE0 and STROBE1
IDE_IOW0# IDE_IOW1#
R24 T25
O O
IDE I/O Write for Channels 0 and 1 IDE_IOW0# is the write signal for Channel 0, and IDE_IOW1# is the read signal for Channel 1. Each signal is asserted on write accesses to corresponding IDE port addresses. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle -- STOP0 and STOP1 Write Cycle -- STOP0 and STOP1
IDE_CS0# IDE_CS1# IDE_IORDY0 IDE_IORDY1
V26 Y26 AD25 AE26
O O I I
IDE Chip Selects The chip select signals are used to select the command block registers in an IDE device. I/O Ready Channels 0 and 1 When deasserted, these signals extend the transfer cycle of any host register access when the device is not ready to respond to the data transfer request. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle -- STROBE0 and STROBE1 Write Cycle -- DMARDY0# and DMARDY1#
IDE_DREQ0 IDE_DREQ1 IDE_DACK0# IDE_DACK1#
AD26 AC24 T26 T24
I I O O
DMA Request Channels 0 and 1 The DREQ is used to request a DMA transfer from the CS5530A. The direction of the transfers are determined by the IDE_IOR/IOW signals. DMA Acknowledge Channels 0 and 1 The DACK# acknowledges the DREQ request to initiate DMA transfers.
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Signal Definitions (Continued)
2.2.8 USB Interface Pin No. V4 Pin Type O Description Power Enable This pin enables the power to a self-powered USB hub. OVER_CUR# W3 I Over Current This pin indicates the USB hub has detected an overcurrent on the USB. D+_PORT1 Y2 I/O USB Port 1 Data Positive This pin is the Universal Serial Bus Data Positive for port 1. D-_PORT1 Y1 I/O USB Port 1 Data Minus This pin is the Universal Serial Bus Data Minus for port 1. D+_PORT2 AA2 I/O USB Port 2 Data Positive This pin is the Universal Serial Bus Data Positive for port 2. D-_PORT2 AA1 I/O USB Port 2 Data Minus This pin is the Universal Serial Bus Data Minus for port 2. VDD_USB AVDD_USB AVSS_USB U2 AB4 AA4 PWR I Analog I Analog Power for USB Analog Power for USB Analog Ground for USB
Signal Name POWER_EN
2.2.9
Game Port and General Purpose I/O Interface Pin No. AD21 Pin Type O Description Game Port Chip Select GPORT_CS# is asserted upon any I/O reads or I/O writes to I/O Port 200h and 201h.
Signal Name GPORT_CS#
GPCS#
AF26
O
General Purpose Chip Select GPCS# is asserted upon any I/O access that matches the I/O address in the General Purpose Chip Select Base Address Register (F0 Index 70h) and the conditions set in the General Purpose Chip Select Control Register (F0 Index 72h).
GPIO7/SA23 GPIO6/SA22 GPIO5/SA21 GPIO4/SA20
AF23 AE23 AC21 AD22
I/O
Limited ISA Mode: General Purpose I/Os 7 through 4 or System Address Bus Lines 23 through 20 These pins can function either as general purpose I/Os or as the upper four bits of the SA bus. Selection is done through F0 Index 43h[6,2]. Refer to GPIO[3:2] signal description for GPIO function description. ISA Master Mode: System Address Bus Lines 23 through 20 These pins function as the four MSB (most significant bits) of the SA bus.
GPIO3 GPIO2
AF24 AF25
I/O I/O
General Purpose I/Os 3 and 2 GPIOs can be programmed to operate as inputs or outputs via F0 Index 90h. As an input, the GPIO can be configured to generate an external SMI. Additional configuration can select if the SMI# is generated on the rising or falling edge. GPIO external SMI generation/edge selection is done in F0 Index 92h and 97h.
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Signal Definitions (Continued)
2.2.9 Game Port and General Purpose I/O Interface (Continued) Pin No. AE24 Pin Type I/O Description General Purpose I/O 1 or Serial Data Input 2 This pin can function either as a general purpose I/O or as a second serial data input pin if two codecs are used in the system. In order for this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). Then setting F3BAR+Memory Offset 08h[21] = 1 selects the pin to function as SDATA_IN2. Refer to GPIO[3:2] signal description for GPIO function description. GPIO0 AC22 I/O General Purpose I/O 0 Refer to GPIO[3:2] signal description for GPIO function description.
Signal Name GPIO1/ SDATA_IN2
2.2.10 Audio Interface Signal Name BIT_CLK Pin No. V2 Pin Type I Description Audio Bit Clock The serial bit clock from the codec. SDATA_OUT V1 O Serial Data I/O This output transmits audio serial data to the codec. SDATA_IN U4 I Serial Data Input This input receives serial data from the codec. SYNC U3 O Serial Bus Synchronization This bit is asserted to synchronize the transfer of data between the CS5530A and the AC97 codec. PC_BEEP V3 O PC Beep Legacy PC/AT speaker output.
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Signal Definitions (Continued)
2.2.11 Display Interface Signal Name Pixel Port PCLK A13 I Pixel Clock This clock is used to sample data on the PIXEL input port. It runs at the graphics DOT clock (DCLK) rate. PIXEL[23:0] Refer to Table 2-3 I Pixel Data Port This is the input pixel data from the processor's display controller. If F4BAR+Memory Offset 00h[29] is reset, the data is sent in RGB 8:8:8 format. Otherwise, the pixel data is sent in RGB 5:6:5 format which has been dithered by the processor. The other eight bits are used in conjunction with VID_DATA[7:0] to provide 16-bit video data. This bus is sampled by the PCLK input. I Display Enable Input This signal qualifies active data on the pixel input port. It is used to qualify active pixel data for all display modes and configurations and is not specific to flat panel display. Display CRT HSYNC C6 I Horizontal Sync Input This is the CRT horizontal sync input from the processor's display controller. It is used to indicate the start of a new video line. This signal is pipelined for the appropriate number of clock stages to remain in sync with the pixel data. A separate output (HSYNC_OUT) is provided to re-drive the CRT and flat panel interfaces. HSYNC_OUT N1 O Horizontal Sync Output This is the horizontal sync output to the CRT. It represents a delayed version of the input horizontal sync signal with the appropriate pipeline delay relative to the pixel data. The pipeline delay and polarity of this signal are programmable. VSYNC B5 I Vertical Sync Input This is the CRT vertical sync input from the processor's display controller. It is used to indicate the start of a new frame. This signal is pipelined for the appropriate number of clock stages to remain in sync with the pixel data. A separate output (VSYNC_OUT) is provided to re-drive the CRT and flat panel interfaces. VSYNC_OUT N2 O Vertical Sync Output This is the vertical sync output to the CRT. It represents a delayed version of the input vertical sync signal with the appropriate pipeline delay relative to the pixel data. The pipeline delay and polarity of this signal are programmable. DDC_SCL M2 O DDC Serial Clock This is the serial clock for the VESA Display Data Channel interface. It is used for monitoring communications. The DDC2B standard is supported by this interface. DDC_SDA M4 I/O DDC Serial Data This is the bidirectional serial data signal for the VESA Display Data Channel interface. It is used to monitor communications. The DDC2B standard is supported by this interface. The direction of this pin can be configured through F4BAR+Memory Offset 04h[24]: 0 = Input; 1 = Output.
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Pin No.
Pin Type
Description
ENA_DISP
B1
GeodeTM CS5530A
Signal Definitions (Continued)
2.2.11 Display Interface (Continued) Signal Name IREF (Video DAC) Pin No. R3 Pin Type I Analog Description VDAC Current Reference Input Connect a 680 ohm resistor between this pin and AVSS (analog ground for Video DAC). External Voltage Reference Pin Connect this pin to a 1.235V voltage reference. Analog Power for Video DAC These pins provide power to the analog portions of the Video DAC. A 47 F capacitor should be connected between the DAC analog power and DAC analog ground. Analog power is AVDD1 (pin U1) and AVDD3 (pin N4). Analog ground is AVSS1 (pin R2) and AVSS5 (pin P2). I Analog Analog Ground for Video DAC These pins provide the ground plane connections to the analog portions of the Video DAC. A 47 F capacitor should be connected between the DAC analog power and DAC analog ground. Analog power is AVDD1 (pin U1) and AVDD3 (pin N4). Analog ground is AVSS1 (pin R2) and AVSS5 (pin P2). O Analog O Analog O Analog Red DAC Output Red analog output. Green DAC Output Green analog output. Blue DAC Output Blue analog output.
EXTVREFIN (Video DAC) AVDD1 (DAC) AVDD2 (VREF) AVDD3 (DAC)
T2
I Analog I Analog
U1 T3 N4
AVSS1 (DAC) AVSS2 (ICAP) AVSS3 (VREF) AVSS4 (ICAP) AVSS5 (DAC) IOUTR (Video DAC) IOUTG (Video DAC) IOUTB (Video DAC) Display TFT/TV FP_DATA17/ MASTER#
R2 R4 T4 P1 P2 P3
P4
R1
F3
O
Limited ISA Mode: Flat Panel Data Port Line 17 Refer to FP_DATA[15:0] signal description.
I
ISA Master Mode: Master Refer to Section 2.2.5 "ISA Bus Interface" on page 28 for this signal's definition.
FP_DATA16/ SA_OE#
H3
O
Limited ISA Mode: Flat Panel Data Port Line 16 Refer to FP_DATA[15:0] signal description.
O
ISA Master Mode: System Address Transceiver Output Enable Refer to Section 2.2.5 "ISA Bus Interface" on page 28 for this signal's definition.
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Signal Definitions (Continued)
2.2.11 Display Interface (Continued) Signal Name FP_DATA[15:0]/ SA[15:0] Pin No. Refer to Table 2-3 Pin Type O Description Limited ISA Mode: Flat Panel Data Port Lines 15 through 0 This is the data port to an attached active matrix TFT panel. This port may optionally be tied to a DSTN formatter chip, LVDS transmitter, or digital NTSC/PAL encoder. F4BAR+Memory Offset 04h[7] enables the flat panel data bus: 0 = FP_DATA[17:0] is forced low 1 = FP_DATA[17:0] is driven based upon power sequence control I/O ISA Master Mode: System Address Bus Lines 15 through 0 These pins function as SA[15:0] and the pins designated as SA/SD[15:0] function only as SD[15:0]. Note that SA[19:16] are dedicated address pins and GPIO[7:4] function as SA[23:20] only. FP_CLK M1 O Limited ISA Mode: Flat Panel Clock This is the clock for the flat panel interface. -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A cannot support TFT flat panels or TV controllers. FP_CLK_EVEN L3 O Limited ISA Mode: Flat Panel Even Clock This is an optional output clock for a set of external latches used to de-multiplex the flat panel data bus into two channels (odd/even). Typically this would be used to interface to a pair of LVDS transmitters driving an XGA resolution flat panel. F4BAR+Memory Offset 04h[12] enables the FP_CLK_EVEN output: 0 = Standard flat panel 1 = XGA flat panel -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_HSYNC C2 I Limited ISA Mode: Flat Panel Horizontal Sync Input This is the horizontal sync input reference from the processor's display controller. The timing of this signal is independent of the standard (CRT) horizontal sync input to allow a different timing relationship between the flat panel and an attached CRT. -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_HSYNC_OUT /SMEMW# E1 O Limited ISA Mode: Flat Panel Horizontal Sync Output This is the horizontal sync for an attached active matrix TFT flat panel. This represents a delayed version of the input flat panel horizontal sync signal with the appropriate pipeline delay relative to the pixel data. ISA Master Mode: System Memory Write Refer to Section 2.2.5 "ISA Bus Interface" on page 28 for this signal's definition.
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GeodeTM CS5530A
Signal Definitions (Continued)
2.2.11 Display Interface (Continued) Signal Name FP_VSYNC Pin No. C1 Pin Type I Description Limited ISA Mode: Flat Panel Vertical Sync Input This is the vertical sync input reference from the processor's display controller. The timing of this signal is independent of the standard (CRT) vertical sync input to allow a different timing relationship between the flat panel and an attached CRT. -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_VSYNC_OUT /SMEMR# E3 O Limited ISA Mode: Flat Panel Vertical Sync Output This is the vertical sync for an attached active matrix TFT flat panel. This represents a delayed version of the input flat panel vertical sync signal with the appropriate pipeline delay relative to the pixel data. ISA Master Mode: System Memory Read Refer to Section 2.2.5 "ISA Bus Interface" on page 28 on for this signal's definition. FP_DISP_ ENA_OUT F2 O Flat Panel Display Enable Output This is the display enable for an attached active matrix TFT flat panel. This signal qualifies active pixel data on the flat panel interface. -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_ENA_VDD L2 O Flat Panel VDD Enable This is the enable signal for the VDD supply to an attached flat panel. It is under the control of power sequence control logic. A transition on bit 6 of the Display Configuration Register (F4BAR+Memory Offset 04h) initiates a power-up/down sequence. -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_ENA_BKL J4 O Flat Panel Backlight Enable Output This is the enable signal for the backlight power supply to an attached flat panel. It is under control of the power sequence control logic. -ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers.
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Signal Definitions (Continued)
2.2.11 Display Interface (Continued) Signal Name Display MPEG VID_DATA[7:0] C12, B12, A12, D11, C11, B13, C13, A11 A6 I Video Data Port This is the input data for a video (MPEG) or graphics overlay in its native form. For video overlay, this data is in an interleaved YUV 4:2:2 format. For graphics overlay, the data is in RGB 5:6:5 format. This port operates at the VID_CLK rate. Pin No. Pin Type Description
VID_CLK
I
Video Clock This is the clock for the video port. This clock is completely asynchronous to the input pixel clock rate.
VID_VAL
B7
I
Video Valid This signal indicates that valid video data is being presented on the VID_DATA input port. If the VID_RDY signal is also asserted, the data will advance.
VID_RDY
B10
O
Video Ready This signal indicates that the CS5530A is ready to receive the next piece of video data on the VID_DATA port. If the VID_VAL signal is also asserted, the data will advance.
2.2.12 DCLK PLL Signal Name PLLTEST Pin No. N23 Pin Type -Description PLLTEST Internal test pin. This pin should not be connected for normal operation. PLLVAA M25 I Analog I Analog I Analog I Analog Analog PLL Power (VDD) PLLVAA is the analog positive rail power connection to the PLL. Analog PLL Ground (VSS) PLLAGD is the analog ground rail connection to the PLL. Digital PLL Power (VDD) This pin is the digital VDD power connection for the PLL. Digital PLL Ground (VSS) This pin is the digital ground (VSS) connection for the PLL.
PLLAGD
N25
PLLDVD
M23
PLLDGN
N26
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Signal Definitions (Continued)
2.2.13 Power, Ground, and No Connects Signal Name VDD Pin No. Refer to Table 2-3 (Total of 17) Refer to Table 2-3 (Total of 38) Refer to Table 2-3 (Total of 20) Pin Type PWR Description 3.3V (nominal) Power Connection Note that the USB power (VDD_USB, AVDD_USB) connections are listed in Section 2.2.8 "USB Interface" on page 33. GND Ground Connection Note that the USB ground (AVSS_USB) connection is listed in Section 2.2.8 "USB Interface" on page 33. -No Connection These lines should be left disconnected. Connecting a pull-up/-down resistor or to an active signal could cause unexpected results and possible malfunctions.
VSS
NC
2.2.14 Internal Test and Measurement Signal Name TEST Pin No. D3 Pin Type I Description Test Mode TEST should be tied low for normal operation.
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Functional Description
All of the major functional blocks interact with the processor through the PCI bus, or via its own direct interface. The major functional blocks are divided out as: * PC/AT Compatibility Logic -- ISA Subtractive Decode -- ISA Bus Interface -- ROM Interface -- Megacells -- I/O Ports 092h and 061h System Control -- Keyboard Interface Function -- External Real-Time Clock Interface * IDE Controller -- IDE Interface Signals -- IDE Configuration Registers * XpressAUDIO -- Subsystem Data Transport Hardware -- VSA Technology Support Hardware * Display Subsystem Extensions -- Video Interface Configuration Registers -- Video Accelerator -- Video Overlay -- Gamma RAM -- Display Interface * Universal Serial Bus Support -- USB PCI Controller -- USB Host Controller -- USB Power Management Note that this Functional Description section of the data book describes many of the registers used for configuration of the CS5530A; however, not all registers are reported in detail. Some tables in the following subsections show only the bits (not the entire register) associated with a specific function being discussed. For access, register, and bit information regarding all CS5530A registers refer to Section 4.0 "Register Descriptions" on page 140.
The Geode CS5530A I/O companion provides many support functions for a GX-series processor (i.e., GX1, GXLV, GXm). This chapter discusses the detailed operations of the CS5530A in two categories: system-level activities and operations/programming of the major functional blocks. The system-level discussion topics revolve around events that affect the device as a whole unit and as an interface with other chips (e.g., processor): Topics include: * Processor Interface -- Display Subsystem Connections -- PSERIAL Pin Interface * PCI Bus Interface -- PCI Initiator -- PCI Target -- Special Bus Cycles-Shutdown/Halt -- PCI Bus Parity -- PCI Interrupt Routing Support -- Delayed Transactions * Resets and Clocks -- Resets -- ISA Clock -- DOT Clock * Power Management -- CPU Power Management -- APM Support -- Peripheral Power Management
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Functional Description (Continued)
3.1 PROCESSOR INTERFACE GeodeTM CS5530A I/O Companion
PSERIAL IRQ13 INTR SMI# SUSP# SUSPA# CPU_RST AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# LOCK# DEVSEL# PERR# SERR# REQ# GNT# PCLK DCLK HSYNC VSYNC FP_HSYNC FP_VSYNC ENA_DISP VID_VAL VID_CLK VID_DATA[7:0] VID_RDY Note PIXEL[23:0] PIXEL[17:0]
The CS5530A interface to a GX-series processor consists of seven miscellaneous connections, the PCI bus interface signals, plus the display controller connections. Figure 3-1 shows the interface requirements. Note that the PC/AT legacy pins NMI, WM_RST, and A20M are all virtual functions executed in SMM (System Management Mode) by the BIOS. * PSERIAL is a one-way serial bus from the processor to the CS5530A used to communicate power management states and VSYNC information for VGA emulation. * IRQ13 is an input from the processor indicating that a floating point error was detected and that INTR should be asserted. * INTR is the level output from the integrated 8259 PICs and is asserted if an unmasked interrupt request (IRQn) is sampled active. * SMI# is a level-sensitive interrupt to the processor that can be configured to assert on a number of different system events. After an SMI# assertion, SMM is entered and program execution begins at the base of the SMM address space. Once asserted, SMI# remains active until the SMI source is cleared. * SUSP# and SUSPA# are handshake pins for implementing CPU Clock Stop and clock throttling. * CPU_RST resets the CPU and is asserted for approximately 9 ms after the negation of POR#. * PCI bus interface signals. * Display subsystem interface connections.
GeodeTM GX-Series Processor
SERIALP IRQ13 INTR SMI# SUSP# SUSPA# RESET AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# LOCK# DEVSEL# PERR# SERR# REQ0# GNT0# PCLK DCLK CRT_HSYNC CRT_VSYNC FP_HSYNC FP_VSYNC ENA_DISP VID_VAL VID_CLK VID_DATA[7:0] VID_RDY
Note:
Refer to Figure 3-3 on page 44 for correct interconnection of PIXEL lines with the processor.
Figure 3-1. Processor Signal Connections
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Functional Description (Continued)
3.1.1 Display Subsystem Connections When a GX-series processor is used in a system with the CS5530A, the need for an external RAMDAC is eliminated. The CS5530A contains the DACs, a video accelerator engine, and the TFT interface. The CS5530A also supports both portable and desktop configurations. Figure 3-2 shows the signal connections for both types of systems.
Figure 3-3 on page 44 details how PIXEL[17:0] on the pro-
cessor connects with PIXEL[23:0] of the CS5530A.
Portable Configuration
Pwr Cntrl Logic VDD 12VBKL ENAB HSYNC VSYNC CLK R[5:0] G[5:0] B[5:0]
PCLK VID_CLK DCLK FP_HSYNC FP_VSYNC ENA_DISP VID_RDY VID_DATA[7:0] VID_VAL CRT_HSYNC CRT_VSYNC
PCLK VID_CLK DCLK FP_HSYNC FP_VSYNC ENA_DISP VID_RDY VID_DATA[7:0] VID_VAL HSYNC VSYNC
FP_ENA_VDD FP_ENA_BKL FP_DISP_ENA_OUT FP_HSYNC_OUT FP_VSYNC_OUT FP_CLK FP_DATA[17:12] FP_DATA[11:6] FP_DATA[5:0]
TFT Flat Panel
PIXEL[17:12] PIXEL[11:6] PIXEL[5:0]
PIXEL[23:18] PIXEL[15:10] PIXEL[7:2]
Note
HSYNC VSYNC CLK R[5:0] G[5:0] B[5:0]
GeodeTM GX-Series Processor
TV NTSC/PAL Encoder
GeodeTM CS5530A I/O Companion
HSYNC_OUT VSYNC_OUT
Pin 13 Pin 14
Pin 3 Pin 2 Pin 1
DDC_SCL DDC_SDA IOUTR IOUTG IOUTB
Pin 15 Pin 12
VGA Port
Note:
Connect PIXEL[17:16] PIXEL[9:8], and PIXEL[1:0] on the CS5530A to ground. See Figure 3-3 "PIXEL Signal Connections" on page 44.
Figure 3-2. Portable/Desktop Display Subsystem Configurations
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Functional Description (Continued)
PIXEL17
PIXEL23 PIXEL22 PIXEL21 PIXEL20 PIXEL19 PIXEL18 PIXEL17 PIXEL16
GeodeTM GX-Series Processor
PIXEL16 PIXEL15 PIXEL14 PIXEL13 PIXEL12
GeodeTM CS5530A I/O Companion
PIXEL11 PIXEL10 PIXEL9 PIXEL8 PIXEL7 PIXEL6
PIXEL15 PIXEL14 PIXEL13 PIXEL12 PIXEL11 PIXEL10 PIXEL9 PIXEL8
PIXEL5 PIXEL4 PIXEL3 PIXEL2 PIXEL1 PIXEL0
PIXEL7 PIXEL6 PIXEL5 PIXEL4 PIXEL3 PIXEL2 PIXEL1 PIXEL0
Figure 3-3. PIXEL Signal Connections
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Functional Description (Continued)
3.1.2 PSERIAL Pin Interface The majority of the system power management logic is implemented in the CS5530A, but a minimal amount of logic is contained within the GX-series processor to provide information that is not externally visible (e.g., graphics controller). The processor implements a simple serial communications mechanism to transmit the CPU status to the CS5530A. The processor accumulates CPU events in an 8-bit register (defined in Table 3-1) which it transmits serially every 1 to 10 s. The packet transmitter holds the serial output pin (PSERIAL) low until the transmission interval timer has elapsed. Once the timer has elapsed, the PSERIAL pin is held high for two clocks to indicate the start of packet transmission. The contents of the Serial Packet Register are then shifted out starting from bit 7 down to bit 0. The PSERIAL pin is held high for one clock to indicate the end of packet transmission and then remains low until the next transmission interval. After the packet transmission is complete, the processor's Serial Packet Register's contents are cleared. The processor's input clock is used as the clock reference for the serial packet transmitter. Once a bit in the register is set, it remains set until the completion of the next packet transmission. Successive events of the same type that occur between packet transmissions are ignored. Multiple unique events between packet transmissions accumulate in this register. The processor transmits the contents of the serial packet only when a bit in the Serial Packet Register is set and the interval timer has elapsed. For more information on the Serial Packet Register referenced in Table 3-1, refer to the appropriate GX-series processor data book.
0
The CS5530A decodes the serial packet after each transmission and performs the power management tasks related to video retrace.
Table 3-1. GX-Series Processor Serial Packet Register
Bit 7 Description Video IRQ: This bit indicates the occurrence of a video vertical sync pulse. This bit is set at the same time that the VINT (Vertical Interrupt) bit gets set in the DC_TIMING_CFG register. The VINT bit has a corresponding enable bit (VIEN) in the DC_TIM_CFG register. CPU Activity: This bit indicates the occurrence of a level 1 cache miss that was not a result of an instruction fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register. Reserved Programmable Address Decode: This bit indicates the occurrence of a programmable memory address decode. The bit is set based on the values of the PM_BASE register and the PM_MASK register. The PM_BASE register can be initialized to any address in the full CPU address range. Video Decode: This bit indicates that the CPU has accessed either the display controller registers or the graphics memory region. This bit has a corresponding enable bit in the PM_CNTRL_TEN.
6
5:2 1
3.1.2.1 Video Retrace Interrupt Bit 7 of the "Serial Packet" can be used to generate an SMI whenever a video retrace occurs within the processor. This function is normally not used for power management but for SoftVGA routines. Setting F0 Index 83h[2] = 1 (bit details on page 163) enables this function. A read only status register located at F1BAR+Memory Offset 00h[5] (bit details on page 183) can be read to see if the SMI was caused by a video retrace event.
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Functional Description (Continued)
3.2 PCI BUS INTERFACE
Note: In a GX-series processor based system, the REQ#/GNT# signals of the CS5530A must connect to the REQ0#/GNT0# of the processor. This configuration ensures that the CS5530A is treated as a non-preemptable PCI master by the processor. The PCI bus interface is compliant with the PCI Bus Specification Rev. 2.1. The CS5530A acts as a PCI target for PCI cycles initiated by the processor or other PCI master devices, or as an initiator for DMA, ISA, IDE, and audio master transfer cycles. It supports positive decode for memory and I/O regions and is the subtractive decode agent on the PCI bus. The CS5530A also generates address and data parity and performs parity checking. A PCI bus arbiter is not part of the CS5530A; however, one is included in the GX-series processor. The PCI Command Register, located at F0 Index 04h (Table 3-2), provides the basic control over the CS5530A's ability to respond and perform PCI bus accesses. 3.2.1 PCI Initiator The CS5530A acts as a PCI bus master on behalf of the DMA controller or ISA, IDE, and audio interfaces. The REQ# and GNT# signals are used to arbitrate for the PCI bus.
The CS5530A asserts REQ# in response to a bus mastering or DMA request for ownership of the PCI bus. GNT# is asserted by the PCI arbiter (i.e., processor) to indicate that access to the PCI bus has been granted to the CS5530A. The CS5530A then issues a grant to the DMA controller. This mechanism prevents any deadlock situations across the bridge. Once granted the PCI bus, the ISA master or DMA transfer commences. If an ISA master executes an I/O access, that cycle remains on the ISA bus and is not forwarded to the PCI bus. The CS5530A performs only single transfers on the PCI bus for legacy DMA cycles.
Table 3-2. PCI Command Register
Bit Description PCI Command Register (R/W) Reset Value = 000Fh
F0 Index 04h-05h 15:10 9 8 7 6 5 4 3 2 1 0 Reserved: Set to 0.
Fast Back-to-Back Enable (Read Only): This function is not supported when the CS5530A is a master. It is always disabled (always reads 0). SERR#: Allow SERR# assertion on detection of special errors. 0 = Disable (Default); 1 = Enable. Wait Cycle Control (Read Only): This function is not supported in the CS5530A. It is always disabled (always reads 0). Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when a parity error is detected. 0 = Disable (Default); 1 = Enable. VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530A. It is always disabled (always reads 0). Memory Write and Invalidate: Allow the CS5530A to do memory write and invalidate cycles, if the PCI Cache Line Size Register (F0 Index 0Ch) is set to 16 bytes (04h). 0 = Disable (Default); 1 = Enable. Special Cycles: Allow the CS5530A to respond to special cycles. 0 = Disable; 1 = Enable (Default). This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle. Bus Master: Allow the CS5530A bus mastering capabilities. 0 = Disable; 1 = Enable (Default). This bit must be set to 1. Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable (Default). I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).
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Functional Description (Continued)
3.2.2 PCI Target The CS5530A positively decodes PCI transactions intended for any internal registers, the ROM address range, and several peripheral and user-defined address ranges. For positive-decoded transactions, the CS5530A is a medium responder. Table 3-3 lists the valid C/BE# encoding for PCI target transactions. The CS5530A acts as the subtractive agent in the system since it contains the ISA bridge functionality. Subtractive decoding ensures that all accesses not positively claimed by PCI devices are forwarded to the ISA bus. The subtractive-decoding sample point can be configured as slow, default, or disabled via F0 Index 41h[2:1]. Table 3-4 shows these programming bits. Figure 3-4 shows the timing for subtractive decoding. Note: I/O accesses that are mis-aligned so as to include address 0FFFFh and at least one byte beyond will "wrap" around to I/O address 0000h.
Table 3-3. PCI Command Encoding
C/BE[3:0]# 0000 0001 Command Type Interrupt Acknowledge Special Cycles: Shutdown, AD[15:0] = 0000 Special Cycles: Halt, AD[15:0] = 0001 0010 0011 010x 0110 0111 100x 1010 1011 1100 1101 1110 1111 I/O Read I/O Write Reserved Memory Read Memory Write Reserved Configuration Read Configuration Write Memory Read Multiple (memory read only) Reserved Memory Read Line (memory read only) Memory Write, Invalidate (memory write)
Table 3-4. Subtractive Decoding Related Bits
Bit Description PCI Function Control Register 2 (R/W) Reset Value = 10h
F0 Index 41h 2:1
Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another device. The CS5530A defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode
PCI_CLK FRAME# IRDY# TRDY# DEVSEL# FAST MED SLOW SUB
Figure 3-4. Subtractive Decoding Timing
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Functional Description (Continued)
3.2.3 Special Bus Cycles-Shutdown/Halt The PCI interface does not pass Special Bus Cycles to the ISA interface, since special cycles by definition have no destination. However, the PCI interface monitors the PCI bus for Shutdown and Halt Special Bus Cycles. Upon detection of a Shutdown Special Bus Cycle, a WM_RST SMI is generated after a delay of three PCI clock cycles. PCI Shutdown Special Cycles are detected when C/BE[3:0]# = 0001 during the address phase and AD[31:0] = xxxx0000h during the data phase. C/BE[3:0]# are also properly asserted during the data phase. Upon detection of a Halt Special Bus Cycle, the CS5530A completes the cycle by asserting TRDY#. PCI Halt Special Bus Cycles are detected when CBE[3:0]# = 0001 during the address phase and AD[31:0] = xxxx0001h during the data phase of a Halt cycle. CBE[3:0]# are also properly asserted during the data phase. 3.2.4 PCI Bus Parity When the CS5530A is the PCI initiator, it generates address parity for read and write cycles. It checks data parity for read cycles and it generates data parity for write cycles. The PAR signal is an even-parity bit that is calculated across 36 bits of AD[31:0] plus C/BE[3:0]#. By default, the CS5530A does not report parity errors. However, the CS5530A detects parity errors during the data phase if F0 Index 04h[6] is set to 1. If enabled and a data parity error is detected, the CS5530A asserts PERR#. It also asserts SERR# if F0 Index 41h[5] is set to 1. This allows NMI generation. The CS5530A also detects parity errors during the address phase if F0 Index 04h[6] is set. When parity errors are detected during the address phase, SERR# is asserted internally. Parity errors are reported to the CPU by enabling the SERR# source in I/O Port 061h (Port B) control register. The CS5530A sets the corresponding error bits in the PCI Status Register (F0 Index 06h[15:14]). Table 3-5 shows these programming bits. If the CS5530A is the PCI master for a cycle and detects PERR# asserted, it generates SERR# internally.
Table 3-5. PERR#/SERR# Associated Register Bits
Bit Description PCI Command Register (R/W) Reset Value = 000Fh
F0 Index 04h-05h 6
Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when a parity error is detected. 0 = Disable (Default); 1 = Enable. PCI Status Register (R/W) Reset Value = 0280h
F0 Index 06h-07h 15 14
Detected Parity Error: This bit is set whenever a parity error is detected. Write 1 to clear. Signaled System Error: This bit is set whenever the CS5530A asserts SERR# active. Write 1 to clear.
F0 Index 41h 5
PCI Function Control Register 2 (R/W)
Reset Value = 10h
PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530A (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system). 0 = Disable; 1 = Enable.
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Functional Description (Continued)
3.2.5 PCI Interrupt Routing Support The CS5530A allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also know in industry terms as PIRQx#) to be mapped internally to any IRQ signal via register programming (shown in Table 3-6). Further details are supplied in Section 3.5.4.4 "PCI Compatible Interrupts" on page 101 regarding edge/level sensitivity selection. 3.2.6 Delayed Transactions The CS5530A supports delayed transactions to prevent slow PCI cycles from occupying too much bandwidth and allows access for other PCI traffic. Note: For systems which have only the GX-series processor and CS5530A on the PCI bus, system performance is improved if delayed transactions are disabled.
F0 Index 42h[5] and F0 Index 43h[1] are used to program this function. Table 3-7 shows these bit formats.
Table 3-6. PCI Interrupt Steering Registers
Bit Description PCI Interrupt Steering Register 1 (R/W) 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 ` Reset Value = 00h 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15
F0 Index 5Ch 7:4 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 3:0 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3
INTB# Target Interrupt: Selects target interrupt for INTB#.
INTA# Target Interrupt: Selects target interrupt for INTA#.
Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. F0 Index 5Dh 7:4 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 3:0 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 PCI Interrupt Steering Register 2 (R/W) 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 Reset Value = 00h 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15
INTD# Target Interrupt: Selects target interrupt for INTD#.
INTC# Target Interrupt: Selects target interrupt for INTC#.
Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility.
Table 3-7. Delay Transaction Programming Bits
Bit Description PCI Function Control Register 3 (R/W) Reset Value = ACh
F0 Index 42h 5 Also see F0 Index 43h[1]. F0 Index 43h 1
Delayed Transactions: Allow delayed transactions on the PCI bus. 0 = Disable; 1 = Enable. USB Shadow Register (R/W) Reset Value = 03h
PCI Retry Cycles: When the CS5530A is a PCI target and the PCI buffer is not empty, allow the PCI bus to retry cycles. 0 = Disable; 1 = Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid.
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Functional Description (Continued)
3.3 RESETS AND CLOCKS
At any state, Power-on/Resume/Reset, the 14.31818 MHz oscillator must be active for the resets to function. 3.3.2 ISA Clock The CS5530A creates the ISACLK from dividing the PCICLK. For ISA compatibility, the ISACLK nominally runs at 8.33 MHz or less. The ISACLK dividers are programmed via F0 Index 50h[2:0] as shown in Table 3-8. The operations of resets and clocks in the CS5530A are described in this section of the Functional Description. 3.3.1 Resets The CS5530A generates two reset signals, PCI_RST# to the PCI bus and CPU_RST to the GX-series processor. These resets are generated after approximately 100 s delay from POR# active as depicted in Figure 3-5.
Table 3-8. ISACLK Divider Bits
Bit Description PIT Control/ISA CLK Divider (R/W) Reset Value = 7Bh
F0 Index 50h 2:0
ISA Clock Divisor: Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for approximately 8 MHz. 000 = Reserved 001 = Divide by two 010 = Divide by three 011 = Divide by four 100 = Divide by five 101 = Divide by six 110 = Divide by seven 111 = Divide by eight
If 25 MHz PCI clock, use setting of 010 (divide by 3). If 30 or 33 MHz PCI clock, use a setting of 011 (divide by 4).
POR#
100 s 9 ms
CPU_RST PCI_RST#
POR# minimum pulse width for CS5530A only (i.e., not a system specification) = 100 s and 14 MHz must be running.
Figure 3-5. CS5530A Reset
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Functional Description (Continued)
3.3.3 DOT Clock The DOT clock (DCLK) is generated from the 14.31818 MHz input (CLK_14MHZ). A combination of a phase locked loop (PLL), linear feedback shift register (LFSR) and divisors are used to generate the desired frequencies for the DOT clock. The divisors and LFSR are configurable through the F4BAR+Memory Offset 24h. The minimum frequency of DCLK is 10 MHz and the maximum is 200 MHz. However, system constraints limit DCLK to 150 MHz when DCLK is used as the graphics subsystem clock. For applications that do not use the GX-series processor's graphics subsystem, this is an available clock for general purpose use. The system clock distribution for a CS5530A/GX-series processor based system is shown in Figure 3-6.
32 KHz for Reset and Power Management TVCLK from TV Controller 14 MHz Clock
GeodeTM CS5530A I/O Companion
M U X
DCLK to GX-Series Processor
DCLK PLL
PCICLK /N ISACLK to ISA Bus
SDRAMCLK to SDRAM
GeodeTM GX-Series Processor
SDRAMCLK to SDRAM SDRAMCLK to SDRAM SDRAMCLK to SDRAM
SUSP_3V from CS5530A
OE#
PCICLK to GX-Series Processor PCICLK to PCI Related Device PCICLK to PCI Bus
Clock Generator
14.318 MHz Crystal
14 MHz Clock to TV Controller 14 MHz Clock to Super I/O 24.576 MHz Clock to AC97 Codec 48 MHz Clock to USB of CS5530A
Figure 3-6. System Clock Distribution
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3.3.3.1 DCLK Programming The PLL contains an input divider (ID), feedback divider (FD) and a post divider (PD). The programming of the dividers is through F4BAR+Memory Offset 24h (see Table 3-9 on page 53). The maximum output frequency is 300 MHz. The output frequency is given by equation #1: Equation #1: DCLK = [CLK_14MHZ * FD] / [PD *ID] Condition: 140 MHz < [DCLK * PD] < 300 MHz Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3: PD is derived from bits [28:24] ID is derived from bits [2:0] Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 is achieved by clearing bit 23 to 0. Example Define Target Frequency: Target frequency = 135 MHz Satisfy the "Condition": (140 MHz < [DCLK * PD] < 300 MHz) 140 MHz < [135 MHz * 2] < 300 MHz Therefore PD = 2 Solve Equation #1: DCLK = [CLK_14MHZ * FD] / [PD *ID] 135 = [14.31818 * FD] / [2 * ID] 135 = [7.159 * FD] / ID 18.86 = FD / ID Guess: ID = 7, Solve for FD FD = 132.02 Solve Equation #2 or #3: FD = 2*N +1 for odd FD FD = 2*N +0 for even FD FD is 132, therefore even 132 = 2*N +0 N = 66 Summarize: PD = 2: Bits [28:24] = 00111 ID = 7: Bits [2:0] = 101 N = 66: Bits [22:12] = 073h (found in Table 3-10), clear bit 23 Result: DCLK = 135 The BIOS has been provided with a complete table of divisor values for supported graphics clock frequencies. Many combinations of divider values and VCO frequencies are possible to achieve a certain output clock frequency. These BIOS values may be adjusted from time to time to meet system frequency accuracy and jitter requirements. For applications that do not use the GX-series processor's graphics subsystem, this is an available clock for general purpose use. The transition from one DCLK frequency to another is not guaranteed to be smooth or bounded; therefore, new divider coefficients should only be programmed while the PLL is off line in a situation where the transition characteristics of the clock are "don't care". The steps below describe (in order) how to change the DCLK frequency. 1) 2) 3) 4) 5) Program the new clock frequency. Program Feedback Reset (bit 31) high and Bypass PLL (bit 8) high. Wait at least 500 s for PLL to settle. Program Feedback Reset (bit 31) low. Program Bypass PLL (bit 8) low.
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Table 3-9. DCLK Configuration Register
Bit Description DOT Clock Configuration Register (R/W) Reset Value = 00000000h
F4BAR+Memory Offset 24h-27h 31 30
Feedback Reset: Reset the PLL postscaler and feedback divider. 0 = Normal operation; 1 = Reset. A more comprehensive reset description is provided in bit 8. Half Clock: 0 = Enable; 1 = Disable. For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post divider output to more closely approximate a 50% output duty cycle.
29 28:24
Reserved: Set to 0. 5-Bit DCLK PLL Post Divisor (PD) Value: Selects value of 1 to 31. 00000 = PD divisor of 8 00001 = PD divisor of 6 00010 = PD divisor of 18 00011 = PD divisor of 4 00100 = PD divisor of 12 00101 = PD divisor of 16 00110 = PD divisor of 24 00111 = PD divisor of 2 *See bit 11 description. 01000 = PD divisor of 10 01001 = PD divisor of 20 01010 = PD divisor of 14 01011 = PD divisor of 26 01100 = PD divisor of 22 01101 = PD divisor of 28 01110 = PD divisor of 30 01111 = PD divisor of 1* 10000 = PD divisor of 9 10001 = PD divisor of 7 10010 = PD divisor of 19 10011 = PD divisor of 5 10100 = PD divisor of 13 10101 = PD divisor of 17 10110 = PD divisor of 25 10111 = PD divisor of 3 11000 = PD divisor of 11 11001 = PD divisor of 21 11010 = PD divisor of 15 11011 = PD divisor of 27 11100 = PD divisor of 23 11101 = PD divisor of 29 11110 = PD divisor of 31 11111 = Reserved
23 22:12 11 10 9 8
Plus 1 (+1): Adds 1 or 0 to FD (DCLK PLL VCO Feedback Divisor) parameter in equation (see Note). 0 = Add 0 to FD; 1 = Add 1 to FD. N: This bit represents "N" in the equation (see Note). It is used to solve the value of FD (DCLK PLL VCO feedback divisor). N can be a value of 1 to 400. For all values of N, refer to Table 3-10 on page 54. CLK_ON: 0 = PLL disable; 1 = PLL enable. If PD = 1 (i.e., bits [28:24] = 01111) the PLL is always enabled and cannot be disabled by this bit. DOT Clock Select: 0 = DCLK; 1 = TV_CLK. Reserved: Set to 0 Bypass PLL: Connects the input of the PLL directly to the output of the PLL. 0 = Normal Operation; 1 = Bypass PLL. If this bit is set to 1, the input of the PLL bypasses the PLL and resets the VCO control voltage, which in turn powers down the PLL. Allow 0.5 ms for the control voltage to be driven to 0V.
7:6 5 4:3 2:0
Reserved: Set to 0. Reserved (Read Only): Write as read Reserved: Set to 0. PLL Input Divide (ID) Value: Selects value of 2 to 9 (see Note). 000 = ID divisor of 2 010 = ID divisor of 4 100 = ID divisor of 6 110 = ID divisor of 8 001 = ID divisor of 3 011 = ID divisor of 5 101 = ID divisor of 7 111 = ID divisor of 9
Note:
To calculate DCLK output frequency: Equation #1: DCLK = [CLK_14MHZ * FD] / [PD *ID] Condition: 140 MHz < [DCLK * PD] < 300 MHz Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3 PD is derived from bits [28:24] ID is derived from bits [2:0]
Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 is achieved by clearing bit 23 to 0.
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Table 3-10. F4BAR+Memory Offset 24h[22:12] Decode (Value of "N")
N 400 399 398 397 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 Reg. Value 33A 674 4E8 1D0 3A0 740 681 502 205 40B 16 2D 5B B7 16F 2DE 5BD 37B 6F6 5EC 3D9 7B2 765 6CB 596 32D 65A 4B4 168 2D0 5A1 343 686 50C 219 433 66 CD 19B 336 66C 4D8 1B0 360 6C0 580 301 602 404 8 11 N 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 Reg. Value 23 47 8F 11F 23E 47D FA 1F5 3EA 7D4 7A9 753 6A7 54E 29D 53B 277 4EF 1DE 3BC 778 6F1 5E2 3C5 78A 715 62B 456 AC 159 2B2 565 2CB 597 32F 65E 4BC 178 2F0 5E1 3C3 786 70D 61B 436 6C D9 1B3 366 6CC 598 N 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 Reg. Value 331 662 4C4 188 310 620 440 80 101 202 405 A 15 2B 57 AF 15F 2BE 57D 2FB 5F7 3EF 7DE 7BD 77B 6F7 5EE 3DD 7BA 775 6EB 5D6 3AD 75A 6B5 56A 2D5 5AB 357 6AE 55C 2B9 573 2E7 5CF 39F 73E 67D 4FA 1F4 3E8 N 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 Reg. Value 7D0 7A1 743 687 50E 21D 43B 76 ED 1DB 3B6 76C 6D9 5B2 365 6CA 594 329 652 4A4 148 290 521 243 487 10E 21C 439 72 E5 1CB 396 72C 659 4B2 164 2C8 591 323 646 48C 118 230 461 C2 185 30A 614 428 50 A1 N 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 Reg. Value 143 286 50D 21B 437 6E DD 1BB 376 6EC 5D8 3B1 762 6C5 58A 315 62A 454 A8 151 2A2 545 28B 517 22F 45F BE 17D 2FA 5F5 3EB 7D6 7AD 75B 6B7 56E 2DD 5BB 377 6EE 5DC 3B9 772 6E5 5CA 395 72A 655 4AA 154 2A8 N 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 Reg. Value 551 2A3 547 28F 51F 23F 47F FE 1FD 3FA 7F4 7E9 7D3 7A7 74F 69F 53E 27D 4FB 1F6 3EC 7D8 7B1 763 6C7 58E 31D 63A 474 E8 1D1 3A2 744 689 512 225 44B 96 12D 25A 4B5 16A 2D4 5A9 353 6A6 54C 299 533 267 4CF N 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Reg. Value 19E 33C 678 4F0 1E0 3C0 780 701 603 406 C 19 33 67 CF 19F 33E 67C 4F8 1F0 3E0 7C0 781 703 607 40E 1C 39 73 E7 1CF 39E 73C 679 4F2 1E4 3C8 790 721 643 486 10C 218 431 62 C5 18B 316 62C 458 B0 N 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reg. Value 161 2C2 585 30B 616 42C 58 B1 163 2C6 58D 31B 636 46C D8 1B1 362 6C4 588 311 622 444 88 111 222 445 8A 115 22A 455 AA 155 2AA 555 2AB 557 2AF 55F 2BF 57F 2FF 5FF 3FF
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3.4 POWER MANAGEMENT
The hardware resources provided by a combined CS5530A/GX-series processor based system support a full-featured power management implementation. The extent to which these resources are employed depends on the application and the discretion of the system designer. Power management resources can be grouped according to the function they enable or support. The major functions are as follows: * CPU Power Management -- On -- Active Idle -- Suspend -- 3 Volt Suspend -- Off -- Save-to-Disk/Save-to-RAM -- Suspend Modulation * APM Support * Peripheral Power Management -- Device Idle Timers and Traps -- General Purpose Timers -- ACPI Timer Register -- General Purpose I/O Pins -- Power Management SMI Status Reporting Registers -- Device Power Management Register Programming Summary Included in the following subsections are details regarding the registers used for configuring power management features. The majority of these registers are directly accessed through the PCI configuration register space designated as Function 0 (F0). However, included in the discussions are references to F1BAR+Memory Offset 10h. This refers to the registers accessed through a base address register in Function 1 (F1) at Index 10h (F1BAR). F1BAR sets the base address for the SMI status and ACPI timer support registers as shown in Table 3-11. 3.4.1 CPU Power Management The three greatest power consumers in a system are the display, hard drive, and CPU. The power management of the first two is relatively straightforward and is discussed in Section 3.4.3 "Peripheral Power Management" on page 63. CPU power management is supported through several mechanisms resulting in five defined system power conditions: * On * Active Idle * Suspend * 3 Volt Suspend * Off There are also three derivative power conditions defined: * Suspend Modulation -- Combination of On and Suspend * Save-to-Disk -- Off with the ability to return back to the exact system condition without rebooting * Save-to-RAM -- Extreme 3 Volt Suspend with only the contents of RAM still powered 3.4.1.1 On System is running and the CPU is actively executing code.
Table 3-11. Base Address Register (F1BAR) for SMI Status and ACPI Timer Support
Bit Description Base Address Register -- F1BAR (R/W) Reset Value = 00000000h
F1 Index 10h-13h
This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h), indicating a 256-byte memory address range. Refer to Table 4-16 for the SMI status and ACPI timer registers bit formats and reset values. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped. Note: The ACPI Timer Count Register is accessible through F1BAR+Memory Offset 1Ch and I/O Port 121Ch. 31:8 7:0 SMI Status/Power Management Base Address Address Range (Read Only)
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3.4.1.2 Active Idle This state is the most powerful power management state because it is an operational state. The CPU has executed a HLT instruction and has asserted the SUSPA# signal. The operating system has control of the entry of this state because the OS has either executed the HLT or made a BIOS call to indicate idle, and the BIOS executed the HLT instruction. The display refresh subsystem is still active but the CPU is not executing code. The clock is stopped to the processing core in this state and considerable power is saved in the processor. The CS5530A takes advantage of this power state by stopping the clock to some of the internal circuitry. This power saving mode can be enabled/disabled by programming F0 Index 96h[4] (see Table 3-12). The CS5530A can still make bus master requests for IDE, audio, USB, and ISA from this state. When the CS5530A or any other device on the PCI bus asserts REQ#, the CPU deasserts SUSPA# for the duration of REQ# activity. Once REQ# has gone inactive and all PCI cycles have stopped, the CPU reasserts SUSPA#. SUSPA# remains active until the CPU receives an INTR or SMI event which ends the CPU halt condition. 3.4.1.3 Suspend This state is similar to the Active Idle state except that the CPU enters this state because the CS5530A asserted SUSP#. The CS5530A deasserts SUSP# when an INTR or SMI event occurs. The Suspend Configuration register is shown in Table 3-12, however, also see the tables listed below for a more complete understanding on configuring the Suspend state. * F0 Index BCh in Table 3-13 "Clock Stop Control Register" on page 57. * Related registers in Table 3-14 "Suspend Modulation Related Registers" on page 59. * F0 Index AEh in Table 3-16 "APM Support Registers" on page 62.
Table 3-12. Suspend Configuration Register
Bit Description Suspend Configuration Register (R/W) Reset Value = 00h
F0 Index 96h 7:5 4 3 2 1 Reserved: Set to 0.
Power Savings Mode: 0 = Enable; 1 = Disable. Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included. Suspend Mode Configuration: "Special 3 Volt Suspend" mode to support powering down a GX-series processor during Suspend. 0 = Disable; 1 = Enable. SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs. 0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA technology and power management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0).
0
Suspend Modulation Feature: 0 = Disable; 1 = Enable. When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h).
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3.4.1.4 3 Volt Suspend This state is a non-operational state. To enter this state the display must have been previously turned off. This state is usually used to put the system into a deep sleep to conserve power and still allow the user to resume where they left off. The CS5530A supports the stopping of the CPU and system clocks for a 3 Volt Suspend state. If appropriately configured, via the Clock Stop Control Register (F0 Index BCh, see Table 3-13), the CS5530A asserts the SUSP_3V pin after it has gone through the SUSP#/SUSPA# handshake. The SUSP_3V pin is a state indicator, indicating that the system is in a low-activity state. This indicator can be used to put the system into a low-power state (the system clock can be turned off). The SUSP_3V pin is intended to be connected to the output enable of a clock generator or buffer chip, so that the clocks to the CPU and the CS5530A (and most other system devices) are stopped. The CS5530A continues to decrement all of its device timers and respond to external SMI interrupts after the input clock has been stopped, as long as the 32 KHz clock continues to oscillate. Any SMI event or unmasked interrupt pin causes the CS5530A to deassert the SUSP_3V pin, restarting the system clocks. As the CPU or other device might include a PLL, the CS5530A holds SUSP# active for a pre-programmed period of delay (the PLL re-sync delay) that varies from 0 to 15 ms. After this period has expired, the CS5530A deasserts SUSP#, stopping Suspend. SMI# is held active for the entire period, so that the CPU reenters SMM when the clocks are restarted. Note: The SUSP_3V pin can be active either high or low. The pin is an input during POR, and is sampled to determine its inactive state. This allows a designer to match the active state of SUSP_3V to the inactive state for a clock driver output enable with a pull-up or pull-down resistor.
3.4.1.5 Off The system is off and there is no power being consumed by the processor or the CS5530A.
Table 3-13. Clock Stop Control Register
Bit Description Clock Stop Control Register (R/W) Reset Value = 00h
F0 Index BCh 7:4
PLL Delay: The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before starting execution. This delay is only invoked if the STP_CLK bit (bit 0) was set. The four-bit field allows values from 0 to 15 ms. 0000 = 0 ms 0001 = 1 ms 0010 = 2 ms 0011 = 3 ms 0100 = 4 ms 0101 = 5 ms 0110 = 6 ms 0111 = 7 ms 1000 = 8 ms 1001 = 9 ms 1010 = 10 ms 1011 = 11 ms 1100 = 12 ms 1101 = 13 ms 1110 = 14 ms 1111 = 15 ms
3:1 0
Reserved: Set to 0. CPU Clock Stop: 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.
Note: This register configures the CS5530A to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system. A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as: 0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped. When a break/resume event occurs, it releases the CPU halt condition. 1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU and system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay programmed in bits [7:4] will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.
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3.4.1.6 Suspend Modulation Suspend Modulation is a derivative of the On and Suspend states and works by asserting and de-asserting the SUSP# pin to the CPU for a configurable period and duty cycle. By modulating the SUSP# pin, an effective reduction in frequency is achieved. Suspend Modulation is the system power management choice of last resort. However, it is an excellent choice for thermal management. If the system is expected to operate in a thermal environment where the processor could overheat, then Suspend Modulation could be used to reduce power consumption in the overheated condition and thus reduce the processor's temperature. When used as a power management state, Suspend Modulation works by assuming that the processor is idle unless external activity indicates otherwise. This approach effectively slows down the processor until external activity indicates a need to run at full speed, thereby reducing power consumption. Suspend Modulation serves as the primary CPU power management mechanism when APM or some other power management software strategy is not present. It can also act as a backup for situations where the power management scheme does not correctly detect an Idle condition in the system. In order to provide high-speed performance when needed, the SUSP# pin modulation can be temporarily disabled any time system activity is detected. When this happens, the processor is "instantly" converted to full speed for a programmed duration. System activities in the CS5530A are defined in hardware as: any unmasked IRQ, accessing Port 061h, SMI, and/or accessing the graphics controller. Since the graphics controller is integrated in the GX-series processor, the indication of graphics activity is sent to the CS5530A via the serial link (see Section 3.1.2 "PSERIAL Pin Interface" on page 45 for more information on serial link) and is automatically decoded. Graphics activity is defined as any access to the VGA register space, the VGA frame buffer, the graphics accelerator control registers and the configured graphics frame buffer. The automatic speedup events (IRQ, SMI, and/or graphics) for Suspend Modulation should be used together with software-controlled speedup registers for major I/O events such as any access to the floppy disk controller, hard disk drive, or parallel/serial ports, since these are indications of major system activities. When major I/O events occur, Suspend Modulation can be temporarily disabled using the procedures described in the following subsections. Bus master internal (Ultra DMA/33, Audio, USB, or ISA) or external requests do not directly affect the Suspend Modulation programming. Configuring Suspend Modulation Control of the Suspend Modulation feature is accomplished using the Suspend Modulation OFF Count Register, the Suspend Modulation ON Count Register, and the Suspend Configuration Register (F0 Index 94h, 95h, and 96h, respectively). The Power Management Enable Register 1 (F0 Index 80h) contains the enables for the individual activity speedup timers. Bit 0 of the Suspend Configuration Register (F0 Index 96h) enables the Suspend Modulation feature. Bit 1 controls how SMI events affect the Suspend Modulation feature. In general this bit should be set to a 1, which causes SMIs to disable Suspend Modulation until it is re-enabled by the SMI handler. The Suspend Modulation OFF and ON Count Registers (F0 Index 94h and 95h) control two 8-bit counters that represent the number of 32 s intervals that the SUSP# pin is asserted and then deasserted to the processor. These counters define a ratio which is the effective frequency of operation of the system while Suspend Modulation is enabled.
Feff = FGX86 x
Off Count On Count + Off Count
The IRQ and Video Speedup Timer Count registers (F0 Index 8Ch and 8Dh) configure the amount of time which Suspend Modulation is disabled when the respective events occur. SMI Speedup Disable If the Suspend Modulation feature is being used for CPU power management, the occurrence of an SMI disables the Suspend Modulation function so that the system operates at full speed while in SMM. There are two methods used to invoke this via bit 1 of the Suspend Configuration Register. If F0 Index 96h[1] = 0: Use the IRQ Speedup Timer (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. If F0 Index 96h[1] = 1: Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The SMI Speedup Disable Register prevents VSA technology software from entering Suspend Modulation while operating in SMM. The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has no effect. Table 3-14 shows the bit formats of the Suspend Modulation related registers
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Table 3-14. Suspend Modulation Related Registers
Bit Description Power Management Enable Register 1 (R/W) Reset Value = 00h
F0 Index 80h 4
Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GX-series processor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power managed using CPU Suspend modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an external VGA access (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) on the PCI bus is also supported. This configuration is nonstandard, but it does allow the power management routines to support an external VGA chip.
3
IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power managed using CPU Suspend modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch). IRQ Speedup Timer Count Register (R/W) Reset Value = 00h
F0 Index 8Ch 7:0
IRQ Speedup Timer Count: This register holds the load value for the IRQ speedup timer. It is loaded into the timer when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer's timebase is 1 ms. This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical value here would be 2 to 4 ms.
F0 Index 8Dh 7:0
Video Speedup Timer Count Register (R/W)
Reset Value = 00h
Video Speedup Timer Count: This register holds the load value for the Video speedup timer. It is loaded into the timer when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and any access to the graphics controller occurs. When a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The video speedup timer's timebase is 1 ms. This speedup mechanism allows instantaneous response to video activity for full speed during video processing calculations. A typical value here would be 50 to 100 ms.
Index 94h 7:0
Suspend Modulation OFF Count Register (R/W)
Reset Value = 00h
Suspend Signal Deasserted Count: This 8-bit value represents the number of 32 s intervals that the SUSP# pin will be deasserted to the GX-series processor. This timer, together with the Suspend Modulation ON Count Register (F0 Index 95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups.
Index 95h 7:0
Suspend Modulation ON Count Register (R/W)
Reset Value = 00h
Suspend Signal Asserted Count: This 8-bit value represents the number of 32 s intervals that the SUSP# pin will be asserted. This timer, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups.
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Table 3-14. Suspend Modulation Related Registers (Continued)
Bit Index 96h 7:5 4 3 2 1 Reserved: Set to 0. Power Savings: 0 = Enable; 1 = Disable. Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included. Suspend Mode Configuration: "Special 3 Volt Suspend" mode to support powering down a GX-series processor during Suspend. 0 = Disable; 1 = Enable. SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs. 0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA technology and power management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). 0 Suspend Modulation Feature: 0 = Disable; 1 = Enable. When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h). F0 Index A8h-A9h 15:0 Video Overflow Count Register (R/W) Reset Value = 0000h Description Suspend Configuration Register (R/W) Reset Value = 00h
Video Overflow Count: Each time the Video Speedup timer (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the 100 ms timer expires before the Video Speedup timer lapses, the Video Overflow Count Register increments and the 100 ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count contained in this register may be combined with other data to determine the type of video accesses present in the system. SMI Speedup Disable Register (Read to Enable) Reset Value = 0000h
F1BAR+Memory Offset 08h-09h 15:0
SMI Speedup Disable: If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register invokes the SMI handler to re-enable Suspend Modulation. The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has no effect.
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3.4.1.7 Save-to-Disk/Save-to-RAM This is a derivative of the Off state. The processor and the CS5530A have the capability to save their complete state. This state information can be saved to a hard disk or to RAM and the system can be turned off. When powered back on, the system can be returned exactly back to the state it was in when the save process began. This means that the system does not have to be rebooted in the traditional sense. In both cases, precautions must be taken in the system design to make sure that there is sufficient space on the hard drive or RAM to store the information. In the case of the RAM, it must also be powered at all times and can not be corrupted when the system is powered off and back on. The PC/AT compatible floppy port is not part of the CS5530A. If a floppy is attached on the ISA bus in a SuperI/O or by some other means, some of the FDC registers are shadowed in the CS5530A because they cannot be safely read. The FDC registers are shown in Table 3-15. Additional shadow registers for other functions are described in: * Table 3-40 "DMA Shadow Register" on page 96 * Table 3-42 "PIT Shadow Register" on page 98 * Table 3-45 "PIC Shadow Register" on page 100 * Table 3-53 "Real-Time Clock Registers" on page 107
Table 3-15. Power Management Shadow Registers
Bit Description Floppy Port 3F2h Shadow Register (RO) Reset Value = xxh
F0 Index B4h 7:0
Floppy Port 3F2h Shadow (Read Only): Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
F0 Index B5h 7:0
Floppy Port 3F7h Shadow Register (RO)
Reset Value = xxh
Floppy Port 3F7h Shadow (Read Only): Last written value of I/O Port 3F7h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
F0 Index B6h 7:0
Floppy Port 1F2h Shadow Register (RO)
Reset Value = xxh
Floppy Port 1F2h Shadow (Read Only): Last written value of I/O Port 1F2h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
F0 Index B7h 7:0
Floppy Port 1F7h Shadow Register (RO)
Reset Value = xxh
Floppy Port 1F7h Shadow (Read Only): Last written value of I/O Port 1F7h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
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3.4.2 APM Support Some IA systems rely solely on an APM (Advanced Power Management) driver for enabling the operating system to power-manage the CPU. APM provides several services which enhance the system power management and is theoretically the best approach; but in its current form, APM is imperfect for the following reasons: * APM is an OS-specific driver, and may not be available for some operating systems. * Application support is inconsistent. Some applications in foreground may prevent Idle calls. * APM does not help with Suspend determination or peripheral power management. The CS5530A provides two entry points for APM support: * Software CPU Suspend control via the CPU Suspend Command Register (F0 Index AEh) * Software SMI entry via the Software SMI Register (F0 Index D0h). This allows the APM BIOS to be part of the SMI handler. These registers are shown in Table 3-16.
Table 3-16. APM Support Registers
Bit F0 Index AEh 7:0 Description CPU Suspend Command Register (WO) Reset Value = 00h
Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] = 0) and all SMI status bits are 0, a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt condition. If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked, allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin. Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wakeup the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events.
F0 Index D0h 7:0
Software SMI Register (WO)
Reset Value = 00h
Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions.
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3.4.3 Peripheral Power Management The CS5530A provides peripheral power management using a combination of device idle timers, address traps, and general purpose I/O pins. Idle timers are used in conjunction with traps to support powering down peripheral devices. Eight programmable GPIO (general purpose I/O) pins are included for external device power control as well as other functions. All I/O addresses are decoded in 16 bits. All memory addresses are decoded in 32 bits. 3.4.3.1 Device Idle Timers and Traps Idle timers are used to power manage a peripheral by determining when the peripheral has been inactive for a specified period of time, and removing power from the peripheral at the end of that time period. Idle timers are provided for the commonly-used peripherals (FDC, IDE, parallel/serial ports, and mouse/keyboard). In addition, there are three user-defined timers that can be configured for either I/O or memory ranges. The Power Management enable bit (F0 Index 80h[1]) enables and disables the power management idle timers. The Trap bit in the same register (F0 Index 80h[2]) enables and disables device I/O traps. The idle timers are 16-bit countdown timers with a 1 second time base, providing a time-out range of 1 to 65536 seconds (1092 minutes) (18 hours). General purpose timers can be programmed to count milliseconds instead of seconds (see Section 3.4.3.2 on page 73 for further information on general purpose timers). When the idle timers are enabled, the timers are loaded from the timer count registers and start to decrement at the next timebase clock, but cannot trigger an interrupt on that cycle. If an idle timer is initially set to 1, it decrements to 0 on the first cycle and continues counting with 65535 on the next cycle. Starting at 2 gives 1 on the first cycle, and 0 on the second cycle, generating the interrupt. Since the timebase is one second, the minimum interval before the next interrupt from this timer is variable, from one to two seconds with a setting of two. The idle timers continue to decrement until one of two possibilities occurs: a bus cycle occurs at that I/O or memory range, or the timer decrements to zero. When a bus cycle occurs, the idle timer is reloaded with its starting value. It then continues to decrement. When the timer decrements to zero, if power management is enabled (F0 Index 80h[0] = 1), the timer generates an SMI. (F0 Index 80h[0] = 0 does not disable these timers from running, but only from generating SMI.) When an idle timer generates an SMI, the SMI handler manages the peripheral power, disables the timer, and enables the trap. The next time an event occurs, the trap generates an SMI. This time, the SMI handler applies power to the peripheral, enables the timer (thus reloading its starting value), and disables the trap. Tables 3-17 through 3-25 show the device associated idle timers and traps programming bits.
Table 3-17. Power Management Global Enabling Bits
Bit Description Power Management Enable Register 1 (R/W) Reset Value = 00h F0 Index 80h 2 1
Traps: Globally enable all power management device I/O traps. 0 = Disable; 1 = Enable. This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h. Idle Timers: Globally enable all power management device idle timers. 0 = Disable; 1 = Enable. Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts. This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h), nor on the General Purpose (UDEFx) Timers (F0 Index 88h-8Bh). This bit must be set for the command to trigger the SUSP#/SUSPA# feature to function (see F0 Index AEh).
0
Power Management: Global power management. 0 = Disable; 1 = Enabled. This bit must be set (1) immediately after POST for some power management resources to function. Until this is done, the command to trigger the SUSP#/SUSPA# feature is disabled (see F0 Index AEh) and all SMI# trigger events listed for F0 Index 84h-87h are disabled. A `0' in this bit does NOT stop the Idle Timers if bit 1 of this register is a `1', but only prevents them from generating an SMI# interrupt. It also has no effect on the UDEF traps.
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Table 3-18. Keyboard/Mouse Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 2 (R/W) Reset Value = 00h
F0 Index 81h 3
Keyboard/Mouse Idle Timer Enable: Load timer from Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3].
F0 Index 82h 3
Power Management Enable Register 3 (R/W)
Reset Value = 00h
Keyboard/Mouse Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[3].
F0 Index 93h 1 0
Miscellaneous Device Control Register (R/W)
Reset Value = 00h
Mouse on Serial Enable: Mouse is present on a serial port. 0 = No; 1 = Yes. (Note) Mouse Port Select: Selects which serial port the mouse is attached to. 0 = COM1; 1 = COM2. (Note)
Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen. These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch). F0 Index 9Eh-9Fh 15:0 Keyboard / Mouse Idle Timer Count Register (R/W) Reset Value = 0000h
Keyboard / Mouse Idle Timer Count: The idle timer loaded from this register determines when the keyboard and mouse are not in use so that the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space when a mouse is enabled on a serial port. The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[3] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3].
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Table 3-19. Parallel/Serial Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 2 (R/W) Reset Value = 00h
F0 Index 81h 2
Parallel/Serial Idle Timer Enable: Load timer from Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2].
F0 Index 82h 2
Power Management Enable Register 3 (R/W)
Reset Value = 00h
Parallel/Serial Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[2].
F0 Index 93h 1 0
Miscellaneous Device Control Register (R/W)
Reset Value = 00h
Mouse on Serial Enable: Mouse is present on a serial port. 0 = No; 1 = Yes. (Note) Mouse Port Select: Selects which serial port the mouse is attached to. 0 = COM1; 1 = COM2. (Note)
Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen. These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch). F0 Index 9Ch-9Dh 15:0 Parallel / Serial Idle Timer Count Register (R/W) Reset Value = 0000h
Parallel / Serial Idle Timer Count: The idle timer loaded from this register is used to determine when the parallel and serial ports are not in use so that the ports can be power managed. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port is not considered here. The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[2] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2].
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Table 3-20. Floppy Disk Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 2 (R/W) Reset Value = 00h
F0 Index 81h 1
Floppy Disk Idle Timer Enable: Load timer from Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, and 3F7 Secondary floppy disk: I/O Port 372h, 373h, 375h, and 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1].
F0 Index 82h 1
Power Management Enable Register 3 (R/W)
Reset Value = 00h
Floppy Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, or 3F7 Secondary floppy disk: I/O Port 372h, 373h, 375h, or 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[1].
F0 Index 93h 7
Miscellaneous Device Control Register (R/W)
Reset Value = 00h
Floppy Drive Port Select: All system resources used to power manage the floppy drive use the primary or secondary FDC addresses for decode. 0 = Primary; 1 = Primary and Secondary. Floppy Disk Idle Timer Count Register (R/W) Reset Value = 0000h
F0 Index 9Ah-9Bh 15:0
Floppy Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the floppy disk drive is not in use so that it can be powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to any of I/O Ports 3F2h, 3F4h, 3F5h, and 3F7h (primary) or 372h, 374h, 375h, and 377h (secondary). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[1] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1].
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Table 3-21. Primary Hard Disk Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 2 (R/W) Reset Value = 00h
F0 Index 81h 0
Primary Hard Disk Idle Timer Enable: Load timer from Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0].
F0 Index 82h 0
Power Management Enable Register 3 (R/W)
Reset Value = 00h
Primary Hard Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[0].
F0 Index 93h 5
Miscellaneous Device Control Register (R/W)
Reset Value = 00h
Partial Primary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as primary hard disk accesses. 0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h 1 = Power management monitors only writes to I/O Port 1F6h and 1F7h
F0 Index 98h-99h 15:0
Primary Hard Disk Idle Timer Count Register (R/W)
Reset Value = 0000h
Primary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the primary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of primary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured primary hard disk's data port (configured in F0 Index 93h[5]). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[0] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0].
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Table 3-22. Secondary Hard Disk Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 4 (R/W) Reset Value = 00h
F0 Index 83h 7
Secondary Hard Disk Idle Timer Enable: Load timer from Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4].
6
Secondary Hard Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[5].
F0 Index 93h 4
Miscellaneous Device Control Register (R/W)
Reset Value = 00h
Partial Secondary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as secondary hard Disk accesses. 0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h 1 = Power management monitors only writes to I/O Port 176h and 177h
F0 Index ACh-ADh 15:0
Secondary Hard Disk Idle Timer Count Register (R/W)
Reset Value = 0000h
Secondary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the secondary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of secondary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured secondary hard disk's data port (configured in F0 Index 93h[4]). The timer uses a 1 second timebase. To enable this timer set F0 Index 83h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4].
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Table 3-23. User Defined Device 1 (UDEF1) Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 4 (R/W) Reset Value = 00h
F0 Index 81h 4
User Defined Device 1 (UDEF1) Idle Timer Enable: Load timer from UDEF1 Idle Timer Count Register (F0 Index A0h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4].
F0 Index 82h 4
Power Management Enable Register 3 (R/W)
Reset Value = 00h
User Defined Device 1 (UDEF1) Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF1 address programming is at F0 Index C0h (base address register), and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[2].
Index A0h-A1h 15:0
User Defined Device 1 Idle Timer Count Register (R/W)
Reset Value = 0000h
User Defined Device 1 (UDEF1) Idle Timer Count: The idle timer loaded from this register determines when the device configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured at F0 Index C0h (base address register) and F0 Index CCh (control register). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[4] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4].
F0 Index C0h-C3h 31:0
User Defined Device 1 Base Address Register (R/W)
Reset Value = 00000000h
User Defined Device 1 (UDEF1) Base Address [31:0]: This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh). User Defined Device 1 Control Register (R/W) Reset Value = 00h
F0 Index CCh 7 6:0
Memory or I/O Mapped: User Defined Device 1 is: 0 = I/O; 1 = Memory. Mask If bit 7 = 0 (I/O): Bit 6 Bit 5 Bits 4:0 If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. 0 = Disable write cycle tracking 1 = Enable write cycle tracking 0 = Disable read cycle tracking 1 = Enable read cycle tracking Mask for address bits A[4:0]
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Table 3-24. User Defined Device 2 (UDEF2) Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 4 (R/W) Reset Value = 00h
F0 Index 81h 5
User Defined Device 2 (UDEF2) Idle Timer Enable: Load timer from UDEF2 Idle Timer Count Register (F0 Index A2h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5].
F0 Index 82h 5
Power Management Enable Register 3 (R/W)
Reset Value = 00h
User Defined Device 2 (UDEF2) Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[3].
F0 Index A2h-A3h 15:0
User Defined Device 2 Idle Timer Count Register (R/W)
Reset Value = 0000h
User Defined Device 2 (UDEF2) Idle Timer Count: The idle timer loaded from this register determines when the device configured as UDEF2 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured at F0 Index C4h (base address register) and F0 Index CDh (control register). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[5] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5].
F0 Index C4h-C7h 31:0
User Defined Device 2 Base Address Register (R/W)
Reset Value = 00000000h
User Defined Device 2 (UDEF2) Base Address [31:0]: This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh). User Defined Device 2 Control Register (R/W) Reset Value = 00h
F0 Index CDh 7 6:0
Memory or I/O Mapped: User Defined Device 2 is: 0 = I/O; 1 = Memory. Mask If bit 7 = 0 (I/O): Bit 6 Bit 5 Bits 4:0 If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. 0 = Disable write cycle tracking 1 = Enable write cycle tracking 0 = Disable read cycle tracking 1 = Enable read cycle tracking Mask for address bits A[4:0]
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Table 3-25. User Defined Device 3 (UDEF3) Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 4 (R/W) Reset Value = 00h
F0 Index 81h 6
User Defined Device 3 (UDEF3) Idle Timer Enable: Load timer from UDEF3 Idle Timer Count Register (F0 Index A4h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6].
F0 Index 82h 6
Power Management Enable Register 3 (R/W)
Reset Value = 00h
User Defined Device 3 (UDEF3) Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[4].
F0 Index A4h-A5h 15:0
User Defined Device 3 Idle Timer Count Register (R/W)
Reset Value = 0000h
User Defined Device 3 (UDEF3) Idle Timer Count: The idle timer loaded from this register determines when the device configured as UDEF3 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured at F0 Index C8h (base address register) and F0 Index CEh (control register). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[6] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6].
F0 Index C8h-CBh 31:0
User Defined Device 3 Base Address Register (R/W)
Reset Value = 00000000h
User Defined Device 3 (UDEF3) Base Address [31:0]: This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh). User Defined Device 3 Control Register (R/W) Reset Value = 00h
F0 Index CEh 7 6:0
Memory or I/O Mapped: User Defined Device 3 is: 0 = I/O; 1 = Memory. Mask If bit 7 = 0 (I/O): Bit 6 Bit 5 Bits 4:0 If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. 0 = Disable write cycle tracking 1 = Enable write cycle tracking 0 = Disable read cycle tracking 1 = Enable read cycle tracking Mask for address bits A[4:0]
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Although not considered as device idle timers, two additional timers are provided by the CS5530A. The Video Idle Timer used for Suspend determination and the VGA Timer used for SoftVGA. These timers and their associated programming bits are listed in Tables 3-26 and 3-27.
Table 3-26. Video Idle Timer and Trap Related Registers
Bit Description Power Management Enable Register 2 (R/W) Reset Value = 00h
F0 Index 81h 7
Video Access Idle Timer Enable: Load timer from Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the video address range (sets bit 0 of the GX-series processor's PSERIAL register) the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7].
F0 Index 82h 7
Power Management Enable Register 3 (R/W)
Reset Value = 00h
Video Access Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX-series processor's PSERIAL register) an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[7].
F0 Index A6h-A7h 15:0
Video Idle Timer Count Register (R/W)
Reset Value = 0000h
Video Idle Timer Count: The idle timer loaded from this register determines when the graphics subsystem has been idle as part of the Suspend determination algorithm. The 16-bit value programmed here represents the period of video inactivity after which the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the graphics controller space. The timer uses a 1 second timebase. In a GX-series processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the CS5530A via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530A also detects accesses to standard VGA space on PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used. To enable this timer set F0 Index 81h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7].
Table 3-27. VGA Timer Related Registers
Bit Description Power Management Enable Register 4 (R/W) Reset Value = 00h
F0 Index 83h 3
VGA Timer Enable: Turn on VGA Timer and generate an SMI when the timer reaches 0. 0 = Disable; 1 = Enable. VGA Timer programming is at F0 Index 8Eh and F0 Index 8Bh[6]. To reload the count in the VGA timer, disable it, optionally change the count value in F0 Index 8Eh[7:0], and reenable it before enabling power management. SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only). Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. The VGA Timer counts whether power management is enabled or disabled.
F0 Index 8Bh 6
General Purpose Timer 2 Control Register (R/W)
Reset Value = 00h
VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh). 0 = 1 ms; 1 = 32 s. VGA Timer Count Register
F0 Index 8Eh 7:0
VGA Timer Load Value: This register holds the load value for the VGA timer. The value is loaded into the timer when the timer is enabled (F0 Index 83h[3] = 1). The timer is decremented with each clock of the configured timebase (F0 Index 8Bh[6]). Upon expiration of the timer, an SMI is generated and the status is reported in F1BAR+Memory Offset 00h/02h[6] (only). Once expired, this timer must be re-initialized by disabling it (F0 Index 83h[3] = 0) and then enabling it (F0 Index 83h[3] = 1). When the count value is changed in this register, the timer must be re-initialized in order for the new value to be loaded. This timer's timebase is selectable as 1 ms (default) or 32 s. (F0 Index 8Bh). Note: Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. It is not affected by the Global Power Management Enable setting at F0 Index 80h[0].
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3.4.3.2 General Purpose Timers The CS5530A contains two general purpose timers, General Purpose Timer 1 (F0 Index 88h) and General Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the Device Idle Timers in that they count down to zero unless re-triggered, and generate an SMI when they reach zero. However, these are 8-bit timers instead of 16 bits, they have a programmable timebase, they are not enabled or disabled by Global Power Management bits F0 Index 80h[1:0], and the events which reload these timers are configurable. These timers are typically used for an indication of system inactivity for Suspend determination. General Purpose Timer 1 can be re-triggered by activity to any of the configured user defined devices, keyboard and mouse, parallel and serial, floppy disk, or hard disk. General Purpose Timer 2 can be re-triggered by a transition on the GPIO7 pin (if GPIO7 is properly configured). Configuration of the GPIO7 is explained in Section 3.4.3.4 "General Purpose I/O Pins" on page 76. The timebase for both general purpose timers can be configured as either 1 second (default) or 1 millisecond. The registers at F0 Index 89h and 8Bh are the control registers for the general purpose timers. Table 3-28 show the bit formats for these registers. After a general purpose timer is enabled or after an event reloads the timer, the timer is loaded with the configured count value. Upon expiration of the timer an SMI is generated and a status flag is set. Once expired, this timer must be re-initialized by disabling and enabling it. The general purpose timer is not loaded immediately, but when the free-running timebase counter reaches its maximum value. Depending on the count at the time, this could be on the next 32 KHz clock (CLK_32K), or after a full count of 32, or 32,768 clocks (approximately 1 msec, or exactly 1 sec). The general purpose timer cannot trigger an interrupt until after the first count. Thus, the minimum time before the next SMI from the timer can be either from 12 msec or 1-2 sec with a setting of 02h.
Table 3-28. General Purpose Timers and Control Registers
Bit Description General Purpose Timer 1 Count Register (R/W) Reset Value = 00h
F0 Index 88h 7:0
General Purpose Timer 1 Count: This register holds the load value for GP Timer 1. This value can represent either an 8bit or 16-bit timer (selected at F0 Index 8Bh[4]). It is loaded into the timer when the timer is enabled (F0 Index 83h[0] =1). Once enabled, an enabled event (configured in F0 Index 89h[6:0]) reloads the timer. The timer is decremented with each clock of the configured timebase. Upon expiration of the timer, an SMI is generated and the top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. The second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0]). Once expired, this timer must be re-initialized by either disabling and enabling it, or writing a new count value here. This timer's timebase can be configured as 1 msec or 1 sec at F0 Index 89h[7].
F0 Index 89h 7 6
General Purpose Timer 1 Control Register (R/W)
Reset Value = 00h
Timebase for General Purpose Timer 1: Selects timebase for GP Timer 1 (F0 Index 88h). 0 = 1 sec; 1 = 1 msec. Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity: 0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF3 reloads GP Timer 1. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register).
5
Re-trigger General Purpose Timer 1 on User Defined Device 2 (UDEF2) Activity: 0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF2 reloads GP Timer 1. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register).
4
Re-trigger General Purpose Timer 1 on User Defined Device 1 (UDEF1) Activity: 0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF1 reloads GP Timer 1. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register)
3
Re-trigger General Purpose Timer 1 on Keyboard or Mouse Activity: 0 = Disable; 1 = Enable Any access to the keyboard or mouse I/O address range (listed below) reloads GP Timer 1. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)
2
Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity: 0 = Disable; 1 = Enable. Any access to the parallel or serial port I/O address range (listed below) reloads the GP Timer 1. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh
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Table 3-28. General Purpose Timers and Control Registers (Continued)
Bit 1 Description Re-trigger General Purpose Timer 1 on Floppy Disk Activity: 0 = Disable; 1 = Enable. Any access to the floppy disk drive address ranges (listed below) reloads GP Timer 1. Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, and 3F7 Secondary floppy disk: I/O Port 372h, 373h, 375h, and 377h The active floppy drive is configured via F0 Index 93h[7]. 0 Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity: 0 = Disable; 1 = Enable. Any access to the primary hard disk drive address range selected in F0 Index 93h[5] reloads GP Timer 1. F0 Index 8Ah 7:0 General Purpose Timer 2 Count Register (R/W) Reset Value = 00h
General Purpose Timer 2 Count: This register holds the load value for GP Timer 2. This value can represent either an 8bit or 16-bit timer (configured in F0 Index 8Bh[5]). It is loaded into the timer when the timer is enabled (F0 Index 83h[1] = 1). Once the timer is enabled and a transition occurs on GPIO7, the timer is re-loaded. The timer is decremented with each clock of the configured timebase. Upon expiration of the timer, an SMI is generated and the top level of status is F1BAR+Memory Offset 00h/02h[9] and the second level of status is reported in F1BAR+Memory Offset 04h/06h[1]). Once expired, this timer must be re-initialized by either disabling and enabling it, or writing a new count value here. For GPIO7 to act as the reload for this timer, it must be enabled as such (F0 Index 8Bh[2]) and be configured as an input (F0 Index 90h[7]). This timer's timebase can be configured as 1 msec or 1 sec in F0 Index 8Bh[3].
F0 Index 8Bh 7 6 5
General Purpose Timer 2 Control Register (R/W)
Reset Value = 00h
Re-trigger General Purpose Timer 1 on Secondary Hard Disk Activity: 0 = Disable; 1 = Enable. Any access to the secondary hard disk drive address range selected in F0 Index 93h[4] reloads GP Timer 1. VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh). 0 = 1 ms; 1 = 32 s. General Purpose Timer 2 Shift: GP Timer 2 is treated as an 8-bit or 16-bit timer. 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah). As a 16-bit timer, the value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 2.
4
General Purpose Timer 1 Shift: GP Timer 1 is treated as an 8-bit or 16-bit timer. 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is that loaded into GP Timer 1 Count Register (F0 Index 88h). As a 16-bit timer, the value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 1.
3 2
Timebase for General Purpose Timer 2: Selects timebase for GP Timer 2 (F0 Index 8Ah). 0 = 1 sec; 1 = 1 msec. Re-trigger General Purpose Timer 2 on GPIO7 Pin Transition: A configured transition on the GPIO7 pin reloads GP Timer 2 (F0 Index 8Ah). 0 = Disable; 1 = Enable. F0 Index 92h[7] selects whether a rising- or a falling-edge transition acts as a reload. For GPIO7 to work here, it must first be configured as an input (F0 Index 90h[7] = 0).
1:0
Reserved: Set to 0.
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3.4.3.3 ACPI Timer Register The ACPI Timer Count Register (F1BAR+Memory Offset 1Ch or a fixed I/O Port at 121Ch) provides the current value of the ACPI timer. The timer counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI is generated when bit 23 toggles. Table 3-29 shows the ACPI Timer Count Register and the ACPI Timer SMI enable bit. V-ACPI I/O Register Space The register space designated as V-ACPI (Virtualized ACPI) I/O does not physically exist in the CS5530A. ACPI is supported in the CS5530A by virtualizing this register space. In order for ACPI to be supported, the V-ACPI module must be included in the BIOS. The register descriptions that follow are supplied here for reference only. Fixed Feature space registers are required to be implemented by all ACPI-compatible hardware. The Fixed Feature registers in the V-ACPI solution are mapped to normal I/O space starting at Offset AC00h. However, the designer can relocate this register space at compile time, hereafter referred to as ACPI_BASE. Registers within the V-ACPI I/O space must only be accessed on their defined boundaries. For example, BYTE aligned registers must not be accessed via WORD I/O instructions, WORD aligned registers must not be accessed as DWORD I/O instructions, etc. Table 3-29 summarizes the registers available in the VACPI I/O Register Space. The "Reference" column gives the table and page number where the bit formats for the registers are located.
Table 3-29. ACPI Timer Related Registers/Bits
Bit Description ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh
F1BAR+Memory Offset 1Ch-1Fh (Note)
ACPI_COUNT (Read Only): This read-only register provides the current value of the ACPI timer. The timer counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. 31:24 23:0 Reserved: Always returns 0. Counter
Note: The ACPI Timer Count Register is also accessible through I/O Port 121Ch. F0 Index 83h 5 Power Management Enable Register 4 (R/W) Reset Value = 00h
ACPI Timer SMI: Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0].
Table 3-30. V-ACPI I/O Register Space Summary
ACPI_ BASE 00h-03h 04h 05h 06h 07h 08h-09h 0Ah-0Bh 0Ch-0Dh 0Eh-0Fh 10h-11h 12h-13h 14h-17h 18h-1Fh Type R/W RO -R/W -R/W R/W R/W R/W R/W R/W R/W -Align 4 1 1 1 1 2 2 4 2 2 2 4 Length 4 1 1 1 1 2 2 2 2 2 2 4 8 Name P_CNT: Processor Control Register P_LVL2: Enter C2 Power State Register Reserved SMI_CMD: OS/BIOS Requests Register (ACPI Enable/ Disable Port) Reserved PM1A_STS: PM1A Status Register PM1A_EN: PM1A Enable Register PM1A_CNT: PM1A Control Register SETUP_IDX: Setup Index Register (V-ACPI internal index register) GPE0_STS: General Purpose Event 0 Status Register GPE0_EN: General Purpose Event 0 Enable Register SETUP_DATA: Setup Data Register (V-ACPI internal data register) Reserved: For Future V-ACPI Implementations Reset Value 00000000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 0000h 00000000h -Reference (Table 4-34) Page 229 Page 229 Page 229 Page 229 Page 229 Page 230 Page 230 Page 230 Page 230 Page 231 Page 231 Page 232 Page 232
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3.4.3.4 General Purpose I/O Pins The CS5530A provides up to eight GPIO (general purpose I/O) pins. Five of the pins (GPIO[7:4] and GPIO1) have alternate functions. Table 3-31 shows the bits used for GPIO pin function selection. Each GPIO pin can be configured as an input or output. GPIO[7:0] can be independently configured to act as edgesensitive SMI events. Each pin can be enabled and configured to be either positive-edge sensitive or negative-edge sensitive. These pins then cause an SMI to be generated when an appropriate edge condition is detected. The power management status registers indicate that a GPIO external SMI event has occurred. The GPIO Pin Direction Register 1 (F0 Index 90h) selects whether the GPIO pin is an input or output. The GPIO Pin Data Register 1 (F0 Index 91h) contains the direct values of the GPIO pins. Write operations are valid only for bits defined as outputs. Reads from this register read the last written value if the pin is an output. GPIO Control Register 1 (F0 Index 92h) configures the operation of the GPIO pins for their various alternate functions. Bits [5:3] set the edge sensitivity for generating an SMI on the GPIO[2:0] (input) pins respectively. Bits [2:0] enable the generation of an SMI. Bit 6 enables GPIO6 to act as the lid switch input. Bit 7 determines which edge transition will cause General Purpose Timer 2 (F0 Index 8Ah) to reload. Table 3-32 shows the bit formats for the GPIO pin configuration and control registers.
Table 3-31. GPIO Pin Function Selection
Bit Description USB Shadow Register (R/W) Reset Value = 03h
F0 Index 43h 6 2
Enable SA20: Pin AD22 configuration: 0 = GPIO4; 1 = SA20. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. Enable SA[23:20]: Pins AF23, AE23, AC21, and AD22 configuration: 0 = GPIO[7:4]; 1 = SA[23:20]. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. Codec Status Register (R/W) Reset Value = 00000000h
F3BAR+Memory Offset 08h-0Bh 21
Enable SDATA_IN2: Pin AE24 functions as: 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0).
Table 3-32. GPIO Pin Configuration/Control Registers
Bit Description GPIO Pin Direction Register 1 (R/W) Reset Value = 00h
F0 Index 90h 7 6 5 4 3 2 1 0
GPIO7 Direction: Selects if GPIO7 is an input or output: 0 = Input; 1 = Output. GPIO6 Direction: Selects if GPIO6 is an input or output: 0 = Input; 1 = Output. GPIO5 Direction: Selects if GPIO5 is an input or output: 0 = Input; 1 = Output. GPIO4 Direction: Selects if GPIO4 is an input or output: 0 = Input; 1 = Output. GPIO3 Direction: Selects if GPIO3 is an input or output: 0 = Input; 1 = Output. GPIO2 Direction: Selects if GPIO2 is an input or output: 0 = Input; 1 = Output. GPIO1 Direction: Selects if GPIO1 is an input or output: 0 = Input; 1 = Output. GPIO0 Direction: Selects if GPIO0 is an input or output: 0 = Input; 1 = Output.
Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins' use as the alternate function. F0 Index 91h 7 6 5 4 3 2 1 0 GPIO Pin Data Register 1 (R/W) Reset Value = 00h
GPIO7 Data: Reflects the level of GPIO7: 0 = Low; 1 = High. GPIO6 Data: Reflects the level of GPIO6: 0 = Low; 1 = High. GPIO5 Data: Reflects the level of GPIO5: 0 = Low; 1 = High. GPIO4 Data: Reflects the level of GPIO4: 0 = Low; 1 = High. GPIO3 Data: Reflects the level of GPIO3: 0 = Low; 1 = High. GPIO2 Data: Reflects the level of GPIO2: 0 = Low; 1 = High. GPIO1 Data: Reflects the level of GPIO1: 0 = Low; 1 = High. GPIO0 Data: Reflects the level of GPIO0: 0 = Low; 1 = High.
Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from this register will read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h.
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Table 3-32. GPIO Pin Configuration/Control Registers (Continued)
Bit Description GPIO Control Register 1 (R/W) Reset Value = 00h
F0 Index 92h 7 6
GPIO7 Edge Sense for Reload of General Purpose Timer 2: Selects which edge transition of GPIO7 causes GP Timer 2 to reload. 0 = Rising; 1 = Falling (Note 2). GPIO6 Enabled as Lid Switch: Allow GPIO6 to act as the lid switch input. 0 = GPIO6; 1 = Lid switch. When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI. The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[3]. If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid's position.
5 4 3 2
GPIO2 Edge Sense for SMI: Selects which edge transition of the GPIO2 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. GPIO1 Edge Sense for SMI: Selects which edge transition of the GPIO1 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. GPIO0 Edge Sense for SMI: Selects which edge transition of the GPIO0 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. Enable GPIO2 as an External SMI Source: Allow GPIO2 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[7].
1
Enable GPIO1 as an External SMI Source: Allow GPIO1 to be an external SMI source and generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 4). 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[6].
0
Enable GPIO0 as an External SMI Source: Allow GPIO0 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 3). 0 = Disable; 1 = Enable (Note 3) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[5].
Notes: 1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). 2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both. 3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the system from Suspend when the clocks are stopped. F0 Index 97h 7 6 5 4 3 Bit 3 must be set to enable this bit. GPIO5 Edge Sense for SMI: Selects which edge transition of the GPIO5 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. GPIO4 Edge Sense for SMI: Selects which edge transition of the GPIO4 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. GPIO3 Edge Sense for SMI: Selects which edge transition of the GPIO3 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 0 must be set to enable this bit. Enable GPIO7 as an External SMI Source: Allow GPIO7 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 7). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[3]. 2 Enable GPIO5 as an External SMI Source: Allow GPIO5 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 6). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[2]. 1 Enable GPIO4 as an External SMI Source: Allow GPIO4 to be an external SMI source and to generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[1]. GPIO Control Register 2 (R/W) Reset Value = 00h
GPIO7 Edge Sense for SMI: Selects which edge transition of the GPIO7 pin generates an SMI. 0 = Rising; 1 = Falling.
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Functional Description (Continued)
Table 3-32. GPIO Pin Configuration/Control Registers (Continued)
Bit 0 Description Enable GPIO3 as an External SMI Source: Allow GPIO3 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[0]. Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h).
Power Management SMI Status Reporting Registers The CS5530A updates status registers to reflect the SMI sources. Power management SMI sources are the device idle timers, address traps, and general purpose I/O pins. Power management events are reported to the processor through the SMI# pin. It is active low. When an SMI is initiated, the SMI# pin is asserted low and is held low until all SMI sources are cleared. At that time, SMI# is deasserted. All SMI sources report to the Top Level SMI Status Register (F1BAR+Memory Offset 02h) and the Top Level SMI Status Mirror Register (F1BAR+Memory Offset 00h). The Top SMI Status and Status Mirror Registers are the top level of hierarchy for the SMI handler in determining the source of an SMI. These two registers are identical except that reading the register at F1BAR+Memory Offset 02h clears the status.
3.4.3.5
Since all SMI sources report to the Top Level SMI Status Register, many of its bits combine a large number of events requiring a second level of SMI status reporting. The second level of SMI status reporting is set up very much like the top level. There are two status reporting registers, one "read only" (mirror) and one "read to clear". The data returned by reading either offset is the same, the difference between the two being that the SMI can not be cleared by reading the mirror register.
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Functional Description (Continued)
Figure 3-7 shows an example SMI tree for checking and clearing the source of general purpose timer and the user defined trap generated SMIs. Table 3-33 on page 80 shows the bit formats of the read to clear Top Level SMI Status Register (F1BAR+Memory Offset 02h). Table 3-34 starting on page 81 shows the bit formats of the read to clear second level SMI status registers. For information regarding the location of the corresponding mirror register, refer to the note in the footer of the register description. Keep in mind, all SMI sources in the CS5530A are reported into the Top Level SMI Status Registers (F1BAR+Memory Offset 00h/02h); however, this discussion is regarding power management SMIs. For details regarding audio SMI events/reporting, refer to Section 3.7.2.2 "Audio SMI Related Registers" on page 123.
SMI# Asserted
SMM software reads SMI Header If Bit X = 1 (External SMI) If Bit X = 0 (Internal SMI)
GeodeTM GX-Series Processor GeodeTM CS5530A
Call internal SMI handler to take appropriate action
F1BAR+Memory Offset 02h Read to Clear to determine top-level source of SMI
SMI Deasserted after all SMI Sources are Cleared (i.e., Top and Second Levels - note some sources may have a Third Level)
Bits [15:10] Other_SMI If bit 9 = 1, Source of SMI is GP Timer or UDEF Trap
F1BAR+Memory Offset 06h Read to Clear to determine second-level source of SMI
Bits 15:6 RSVD Bit 5 PCI_TRP_SMI Bit 4 UDEF3_TRP_SMI Bit 3 UDEF2_TRP_SMI Take Appropriate Action
Bit 9 GTMR_TRP_SMI
Bits [8:0] Other_SMI
Bit 2 UDEF1_TRP_SMI Bit 1 GPT2_SMI Bit 0 GPT1_SMI
Top Level
Second Level
Figure 3-7. General Purpose Timer and UDEF Trap SMI Tree Example
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Functional Description (Continued)
Table 3-33. Top Level SMI Status Register (Read to Clear)
Bit Description Top Level SMI Status Register (RC) Reset Value = 0000h
F1BAR+Memory Offset 02h-03h 15
Suspend Modulation Enable Mirror (Read to Clear): This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h) must be cleared on exit. SMI Source is USB (Read to Clear): SMI was caused by USB activity? 0 = No; 1 = Yes. SMI generation is configured in F0 Index 42h[7:6]. SMI Source is Warm Reset Command (Read to Clear): SMI was caused by Warm Reset command? 0 = No; 1 = Yes. SMI Source is NMI (Read to Clear): SMI was caused by NMI activity? 0 = No; 1 = Yes. Reserved (Read to Clear): Always reads 0. SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read to Clear): SMI was caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register Space? 0 = No; 1 = Yes. The next level of status is found at F1BAR+Memory Offset 04h/06h. SMI Source is Software Generated (Read to Clear): SMI was caused by software? 0 = No; 1 = Yes. SMI on an A20M# Toggle (Read to Clear): SMI was caused by an access to either Port 092h or the keyboard command which initiates an A20M# SMI? 0 = No; 1 = Yes. This method of controlling the internal A20M# in the GX-series processor is used instead of a pin. SMI generation enabling is at F0 Index 53h[0].
14 13 12 11:10 9
8 7
6
SMI Source is a VGA Timer Event (Read to Clear): SMI was caused by the expiration of the VGA Timer (F0 Index 8Eh)? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[3]. SMI Source is Video Retrace (IRQ2) (Read to Clear): SMI was caused by a video retrace event as decoded from the serial connection (PSERIAL register, bit 7) from the GX-series processor? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[2]. Reserved (Read to Clear): Always reads 0. SMI Source is Audio Interface (Read to Clear): SMI was caused by the audio interface? 0 = No; 1 = Yes. The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h. SMI Source is Power Management Event (Read to Clear): SMI was caused by one of the power management resources? 0 = No; 1 = Yes. The next level of status is found at F0 Index 84h-87h/F4h-F7h. Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9.
5
4:2 1 0
Note: Reading this register clears all the SMI status bits. Note that bits 9, 1, and 0 have another level (second) of status reporting. A read-only "Mirror" version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.
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Table 3-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear)
Bit Description Reset Value = 0000h
F1BAR+Memory Offset 06h-07h Second Level Gen. Traps/Timers SMI Status Register (RC) 15:6 5 Reserved (Read to Clear)
PCI Function Trap (Read to Clear): SMI was caused by a trapped configuration cycle (listed below)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. Trapped access to F0 PCI header registers other than Index 40h-43h; SMI generation enabling is at F0 Index 41h[0]. Trapped access to F1 PCI header registers; SMI generation enabling is at F0 Index 41h[3]. Trapped access to F2 PCI header registers; SMI generation enabling is at F0 Index 41h[6]. Trapped access to F3 PCI header registers; SMI generation enabling is at F0 Index 42h[0]. Trapped access to F4 PCI header registers; SMI generation enabling is at F0 Index 42h[1].
4
SMI Source is Trapped Access to User Defined Device 3 (Read to Clear): SMI was caused by a trapped I/O or memory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[6].
3
SMI Source is Trapped Access to User Defined Device 2 (Read to Clear): SMI was caused by a trapped I/O or memory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[5].
2
SMI Source is Trapped Access to User Defined Device 1 (Read to Clear): SMI was caused by a trapped I/O or memory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[4].
1
SMI Source is Expired General Purpose Timer 2 (Read to Clear): SMI was caused by the expiration of General Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[1].
0
SMI Source is Expired General Purpose Timer 1 (Read to Clear): SMI was caused by the expiration of General Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[0].
Note: Reading this register clears all the SMI status bits. A read-only "Mirror" version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.
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Functional Description (Continued)
Table 3-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued)
Bit Description Second Level Power Management Status Register 1 (RC) Reset Value = 84h
F0 Index F4h 7:5 4 Reserved
Game Port SMI Status (Read to Clear): SMI was caused by a R/W access to game port (I/O Port 200h and 201h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. Game Port Read SMI generation enabling is at F0 Index 83h[4]. Game Port Write SMI generation enabling is at F0 Index 53h[3].
3
GPIO7 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO7 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[3].
2
GPIO5 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO5 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[2].
1
GPIO4 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO4 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[1].
0
GPIO3 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO3 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[0].
Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on various power-management SMI events. Reading this register clears the SMI status bits. A readonly (mirror) version of this register exists at F0 Index 84h.
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Table 3-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued)
Bit Description Second Level Power Management Status Register 2 (RC) Reset Value = 00h
F0 Index F5h 7
Video Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Video Idle Timer Count Register (F0 Index A6h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[7].
6
User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[6].
5
User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF2 Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[5].
4
User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF1 Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[4].
3
Keyboard/Mouse Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[3].
2
Parallel/Serial Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[2].
1
Floppy Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Floppy Disk Idle Timer Count Register (F0 Index 9Ah)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[1].
0
Primary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Primary Hard Disk Idle Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[0].
Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the duration configured in the Idle Timer Count register for that device, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 85h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead.
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Functional Description (Continued)
Table 3-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued)
Bit Description Second Level Power Management Status Register 3 (RC) Reset Value = 00h
F0 Index F6h 7
Video Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the Video I/O Trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[7].
6 5
Reserved (Read Only) Secondary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the secondary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[6].
4
Secondary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Hard Disk Idle Timer Count Register (F0 Index ACh)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[7].
3
Keyboard/Mouse Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the keyboard or mouse? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[3].
2
Parallel/Serial Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to either the serial or parallel ports? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[2].
1
Floppy Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the floppy disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[1].
0
Primary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the primary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[0].
Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the device while the trap was enabled, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F0 Index 86h may be read instead.
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Functional Description (Continued)
Table 3-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued)
Bit Description Second Level Power Management Status Register 4 (RO/RC) Reset Value = 00h
F0 Index F7h 7
GPIO2 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO2 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[2].
6
GPIO1 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO1 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[1].
5
GPIO0 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO0 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[0].
4 3
Lid Position (Read Only): This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid switch indicator, this bit reflects the state of the pin. Lid Switch SMI Status (Read to Clear): SMI was caused by a transition on the GPIO6 (lid switch) pin? 0 = No; 1 = Yes. For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index 92h[6] =1).
2
Codec SDATA_IN SMI Status (Read to Clear): SMI was caused by an AC97 codec producing a positive edge on SDATA_IN? 0 = No; 1 = Yes. This is the second level of status is reporting. The top level status is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 80h[5].
1
RTC Alarm (IRQ8) SMI Status (Read to Clear): SMI was caused by an RTC interrupt? 0 = No; 1 = Yes. This SMI event can only occur while in 3V Suspend and RTC interrupt occurs. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
0
ACPI Timer SMI Status (Read to Clear): SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation configuration is at F0 Index 83h[5].
Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 87h.
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Functional Description (Continued)
3.4.3.6 Device Power Management Register Programming Summary Table 3-35 provides a programming register summary of figuration Registers - Function 0" on page 153 and Section the device idle timers, address traps, and general purpose 4.3.2 "SMI Status and ACPI Timer Registers - Function 1" I/O pins. For complete bit information regarding the regison page 182. ters listed in Table 3-35, refer to Section 4.3.1 "Bridge Con-
Table 3-35. Device Power Management Programming Summary
Located at F0 Index xxh Unless Otherwise Noted Device Power Management Resource Global Timer Enable Keyboard / Mouse Idle Timer Parallel / Serial Idle Timer Floppy Disk Idle Timer Video Idle Timer (Note 1) VGA Timer (Note 2) Primary Hard Disk Idle Timer Secondary Hard Disk Idle Timer User Defined Device 1 Idle Timer User Defined Device 2 Idle Timer User Defined Device 3 Idle Timer Global Trap Enable Keyboard / Mouse Trap Parallel / Serial Trap Floppy Disk Trap Video Access Trap Primary Hard Disk Trap Secondary Hard Disk Trap User Defined Device 1 Trap User Defined Device 2 Trap User Defined Device 3 Trap General Purpose Timer 1 General Purpose Timer 2 GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO0 Pin Suspend Modulation OFF/ON Video Speedup IRQ Speedup Enable 80h[1] 81h[3] 81h[2] 81h[1] 81h[7] 83h[3] 81h[0] 83h[7] 81h[4] 81h[5] 81h[6] 80h[2] 82h[3] 82h[2] 82h[1] 82h[7] 82h[0] 83h[6] 82h[4] 82h[5] 82h[6] 83h[0] 83h[1] N/A N/A N/A N/A N/A N/A N/A N/A 96h[0] 80h[4] 80h[3] N/A 93h[1:0] 93h[1:0] 9Ah[15:0], 93h[7] A6h[15:0] 8Eh[7:0] 98h[15:0], 93h[5] ACh[15:0], 93h[4] A0h[15:0], C0h[31:0], CCh[7:0] A2h[15:0], C4h[31:0], CDh[7:0] A4h[15:0], C8h[31:0], CEh[7:0] N/A 9Eh[15:0] 93h[1:0] 9Ch[15:0], 93h[1:0] 93h[7] N/A 93h[5] 93h[4] C0h[31:0], CCh[7:0] C4h[31:0], CDh[7:0] C8h[31:0], CEh[7:0] 88h[7:0], 89h[7:0], 8Bh[4] 8Ah[7:0], 8Bh[5,3,2] 90h[7], 91h[7], 92h[7], 97h[7,3] 90h[6], 91h[6], 92h[6] 90h[5], 91h[5], 97h[6,2] 90h[4], 91h[4], 97h[5,1] 90h[3], 91h[3], 97h[4,0] 90h[2], 91h[2], 92h[5,2] 90h[1], 91h[1] 92h[4,1] 90h[0], 91h[0], 92h[3,0] 94h[7:0]/95h[7:0] 8Dh[7:0] 8Ch[7:0] Configuration Second Level SMI Status/No Clear N/A 85h[3] 85h[2] 85h[1] 85h[7] F1BAR+Memory Offset 00h[6] 85h[0] 86h[4] 85h[4] 85h[5] 85h[6] N/A 86h[3] 86h[2] 86h[1] 86h[7] 86h[0] 86h[5] F1BAR+Memory Offset 04h[2] F1BAR+Memory Offset 04h[3] F1BAR+Memory Offset 04h[4] F1BAR+Memory Offset 04h[0] F1BAR+Memory Offset 04h[1] 91h[7] 87h[4,3], 91h[6] 91h[5] 91h[4] 91h[3] 87h[7], 91h[2] 87h[6], 91h[1] 87h[5], 91h[0] N/A A8h[15:0] N/A Second Level SMI Status/With Clear N/A F5h[3] F5h[2] F5h[1] F5h[7] F1BAR+Memory Offset 02h[6] F5h[0] F6h[4] F5h[4] F5h[5] F5h[6] N/A F6h[3] F6h[2] F6h[1] F6h[7] F6h[0] F6h[5] F1BAR+Memory Offset 06h[2] F1BAR+Memory Offset 06h[3] F1BAR+Memory Offset 06h[4] F1BAR+Memory Offset 06h[0] F1BAR+Memory Offset 06h[1] N/A F7h[4,3] N/A N/A N/A F7h[7] F7h[6] F7h[5] N/A N/A N/A
Note: 1. This function is used for Suspend determination. 2. This function is used for SoftVGA, not power management. It is not affected by Global Power Enable.
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Functional Description (Continued)
3.5 PC/AT COMPATIBILITY LOGIC
* I/O Ports 092h and 061h System Control -- I/O Port 092h System Control -- I/O Port 061h System Control -- SMI Generation for NMI * Keyboard Interface Function -- Fast Keyboard Gate Address 20 and CPU Reset * External Real-Time Clock Interface The following subsections give a detailed description for each of these functions. 3.5.1 ISA Subtractive Decode The CS5530A provides an ISA bus controller. The CS5530A is the default subtractive-decoding agent, and forwards all unclaimed memory and I/O cycles to the ISA interface. For reads and writes in the first 1 MB of memory (i.e., A23:A20 set to 0), MEMR# or MEMW# respectively will be asserted. However, the CS5530A can be configured using F0 Index 04h[1:0] to ignore either I/O, memory, or all unclaimed cycles (subtractive decode disabled, F0 Index 41h[2:1] = 1x). Table 3-36 shows these programming bits. The CS5530A's PC/AT compatibility logic provides support for the standard PC architecture. This subsystem also provides legacy support for existing hardware and software. Support functions for the GX-series processor provided by these subsystems include: * ISA Subtractive Decode * ISA Bus Interface -- Delayed PCI Transactions -- Limited ISA and ISA Master Modes * ROM Interface * Megacells -- Direct Memory Access (DMA) -- Programmable Interval Timer -- Programmable Interrupt Controller -- PCI Compatible Interrupts
Table 3-36. Cycle Configuration Bits
Bit Description PCI Command Register (R/W) Reset Value = 000Fh
F0 Index 04h-05h 1 0
Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable (Default). I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable (Default). PCI Function Control Register 2 (R/W) Reset Value = 10h
F0 Index 41h 2:1
Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another device. The CS5530A defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode
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Functional Description (Continued)
3.5.2 ISA Bus Interface The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write results in two 16-bit ISA transactions or four 8bit ISA transactions. The ISA controller gathers the data from multiple ISA read cycles and returns TRDY# only after all of the data can be presented to the PCI bus at the same time. SA[23:0] are a concatenation of ISA LA[23:17] and SA[19:0] and perform equivalent functionality at a reduced pin count. Figure 3-8 shows the relationship between a PCI cycle and the corresponding ISA cycle generated.
PCI_CLK ISACLK FRAME# IRDY# TRDY# STOP# AD[31:0] (Read) AD[31:0] (Write) BALE IOR#/IOW# MEMR#/MEMW#
Figure 3-8. Non-Posted PCI-to-ISA Access
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3.5.2.1 Delayed PCI Transactions If PCI delayed transactions are enabled (F0 Index 42h[5] = 1) multiple PCI cycles occur for every slower ISA cycle. Figure 3-9 shows the relationship of PCI cycles to an ISA cycle with PCI delayed transactions enabled. See Section 3.2.6 "Delayed Transactions" on page 49 for additional information.
REQ#
GNT#
FRAME# 1 PCI IRDY# 1 TRDY# 2 1
STOP# 1
BALE ISA IOR# 3 1 - Delay 2 - IDE bus master - starts and completes 3 - End of ISA cycle
Figure 3-9. PCI to ISA Cycles with Delayed Transaction Enabled
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Functional Description (Continued)
3.5.2.2 Limited ISA and ISA Master Modes The CS5530A supports two modes on the ISA interface. The default mode of the ISA bus is a fully functional ISA mode, but it does not support ISA masters, as shown in Figure 3-10 "Limited ISA Mode". When in this mode, the address and data buses are multiplexed together, requiring an external latch to latch the lower 16 bits of address of the ISA cycle. The signal SA_LATCH is generated when the data on the SA/SD bus is a valid address. Additionally, the upper four address bits, SA[23:20], are multiplexed on GPIO[7:4]. The second mode of the ISA interface supports ISA bus masters, as shown in Figure 3-11. When the CS5530A is placed in the ISA Master mode, a large number of pins are redefined as shown in Table 3-37. In this mode of operation, the CS5530A cannot support TFT flat panels or TV controllers, since most of the signals used to support these functions have been redefined. This mode is required if ISA slots or ISA masters are used. ISA master cycles are only passed to the PCI bus if they access memory. I/O accesses are left to complete on the ISA bus. The mode of operation is selected by the strapping of pin P26 (INTR): * ISA Limited Mode -- Strap pin P26 (INTR) low through a 10-kohm resistor. * ISA Master Mode -- Strap pin P26 (INTR) high through a 10-kohm resistor. F0 Index 44h[7] (bit details on page 156) reports the strap value of the INTR pin (pin P26) during POR: 0 = ISA Limited; 1 = ISA Master. This bit can be written after POR# deassertion to change the ISA mode selected. Writing to this bit is not recommended due to the actual strapping done on the board. ISA memory and ISA refresh cycles are not supported by the CS5530A, although, the refresh toggle bit in I/O Port 061h still exists for software compatibility reasons.
Table 3-37. Signal Assignments
Pin No. AD15 AE25, AD24, AE22, AE21, AF21, AC20, AD19, AF19, AF4, AF5, AD5, AF6, AC6, AD9, AE6, AE9 H2, K1, K2, L1, D1, E2, F1, G1, G3, G4, G2, H1, J1, J3, J2, K3 H3 F3 E1 E3 AF3 (Note) AD4 (Note) AF23, AE23, AC21, AD22 Note: Limited ISA Mode SA_LATCH SA[15:0]/SD[15:0] ISA Master Mode SA_DIR SD[15:0]
FP_DATA[15:0]
SA[15:0]
FP_DATA[16] FP_DATA[17] FP_HSYNC_OUT FP_VSYNC_OUT SMEMW# SMEMR# GPIO[7:4] SA[23:20]
SA_OE# MASTER# SMEMW# SMEMR# RTCCS# RTCALE SA[23:20]
If Limited ISA Mode of operation has been selected, SMEMW# and SMEMR# can be output on these pins by programming F0 Index 53[2] = 0 (bit details on page 157).
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Functional Description (Continued)
GeodeTM CS5530A
1
ISA Control2
ISA Device
SD[15:0]
GPIO[7:4]/SA[23:20] SA[19:16] SA[15:0]/SD[15:0] INTR 10K SA_LATCH/SA_DIR
3
SA[23:20] SA[19:16] D Q
SA[15:0]
74F373x2 G OC
Notes: 1. F0 Index 43h[2] controls GPIO[7:4]/SA[23:20]. 2. These signals are: MEMW#, MEMR#, IOR#, IOW#, TC, AEN, DREQ[7:5, 3:0], DACK[7:5, 3:0]#, MEMCS16#, ZEROWS#, SBHE#, IOCS16#, IOCHRDY, ISACLK. 3. This resistor is used at boot time to determine the mode of the ISA bus.
Figure 3-10. Limited ISA Mode
ISA Control2 FP_VSYNC_OUT/SMEMR# FP_HSYNC_OUT/SMEMW# 3.3V/5V 330 FP_DATA17/MASTER#
1
SMEMR# SMEMW#
MASTER# SA[23:20] SA[19:16] SA[15:0] 5.0V
GPIO[7:4]/SA[23:20] SA[19:16]
FP_DATA[15:0]/SA[15:0]
GeodeTM CS5530A
INTR
10K3 SD[15:0]
ISA Master
SA[15:0]_SD[15:0]/SD[15:0]
Notes: 1. When strapped for ISA Master mode, GPIO[7:4]/SA[23:20] are set to SA[23:20] and the settings in F0 Index 43h[2] are invalid. 2. These signals are: MEMW#, MEMR#, IOR#, IOW#, TC, AEN, DREQ[7:5, 3:0], DACK[7:5, 3:0]#, MEMCS16#, ZEROWS#, SBHE#, IOCS16#, IOCHRDY, ISACLK. 3. This resistor is used at boot time to determine the mode of the ISA bus.
Figure 3-11. ISA Master Mode
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Functional Description (Continued)
3.5.2.3 ISA Bus Data Steering The CS5530A performs all of the required data steering from SD[7:0] to SD[15:0] during normal 8-bit ISA cycles, as well as during DMA and ISA master cycles. It handles data transfers between the 32-bit PCI data bus and the ISA bus. 8/16-bit devices can reside on the ISA bus. Various PCcompatible I/O registers, DMA controller registers, interrupt controller registers, and count registers (for loading timers) lie on the on-chip I/O data bus. Either the PCI bus master or the DMA controllers can become the bus owner. When the PCI bus master is the bus owner, the CS5530A data steering logic provides data conversion necessary for 8/16/32-bit transfers to and from 8/16-bit devices on either the ISA bus or the 8-bit registers on the on-chip I/O data bus. When PCI data bus drivers of the CS5530A are tristated, data transfers between the PCI bus master and PCI bus devices are handled directly via the PCI data bus. When the DMA requestor is the bus owner, the CS5530A allows 8/16-bit data transfer between the ISA bus and the PCI data bus. 3.5.2.4 I/O Recovery Delays In normal operation, the CS5530A inserts a delay between back-to-back ISA I/O cycles that originate on the PCI bus. The default delay is four ISACLK cycles. Thus, the second of consecutive I/O cycles is held in the ISA bus controller until this delay count has expired. The delay is measured between the rising edge of IOR#/IOW# and the falling edge of BALE. This delay can be adjusted to a greater delay through the ISA I/O Recovery Control Register (F0 Index 51h, see Table 3-38). Note: This delay is not inserted for a 16-bit ISA I/O access that is split into two 8-bit I/O accesses.
Table 3-38. I/O Recovery Programming Register
Bit Description ISA I/O Recovery Control Register (R/W) Reset Value = 40h
F0 Index 51h 7:4
8-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 ISA clock 0001 = 2 ISA clocks 0010 = 3 ISA clocks 0011 = 4 ISA clocks 0100 = 5 ISA clocks 0101 = 6 ISA clocks 0110 = 7 ISA clocks 0111 = 8 ISA clocks 1000 = 9 ISA clocks 1001 = 10 ISA clocks 1010 = 11 ISA clocks 1011 = 12 ISA clocks 1100 = 13 ISA clocks 1101 = 14 ISA clocks 1110 = 15 ISA clocks 1111 = 16 ISA clocks
3:0
16-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 ISA clock 0001 = 2 ISA clocks 0010 = 3 ISA clocks 0011 = 4 ISA clocks 0100 = 5 ISA clocks 0101 = 6 ISA clocks 0110 = 7 ISA clocks 0111 = 8 ISA clocks 1000 = 9 ISA clocks 1001 = 10 ISA clocks 1010 = 11 ISA clocks 1011 = 12 ISA clocks 1100 = 13 ISA clocks 1101 = 14 ISA clocks 1110 = 15 ISA clocks 1111 = 16 ISA clocks
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3.5.2.5 ISA DMA DMA transfers occur between ISA I/O peripherals and system memory. The data width can be either 8 or 16 bits. Out of the seven DMA channels available, four are used for 8bit transfers while the remaining three are used for 16-bit transfers. One BYTE or WORD is transferred in each DMA cycle. Note: The CS5530A does not support DMA transfers to ISA memory. PCI arbiter. After the PCI bus has been granted, the respective DACK# is driven active. The CS5530A generates PCI memory read or write cycles in response to a DMA cycle. Figures 3-12 and 3-13 are examples of DMA memory read and memory write cycles. Upon detection of the DMA controller's MEMR# or MEMW# active, the CS5530A starts the PCI cycle, asserts FRAME#, and negates an internal IOCHRDY. This assures the DMA cycle does not complete before the PCI cycle has provided or accepted the data. IOCHRDY is internally asserted when IRDY# and TRDY# are sampled active.
The ISA DMA device initiates a DMA request by asserting one of the DRQ[7:5, 3:0] signals. When the CS5530A receives this request, it sends a bus grant request to the
PCICLK ISACLK MEMR# IOW# SD[15:0] IOCHRDY FRAME# AD[31:0] IRDY# TRDY#
Figure 3-12. ISA DMA Read from PCI Memory
PCICLK ISACLK MEMW# IOR# SD[15:0] IOCHRDY FRAME# AD[31:0] IRDY# TRDY#
Figure 3-13. ISA DMA Write To PCI Memory
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Functional Description (Continued)
3.5.3 ROM Interface The CS5530A positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000hFFFFFFFFh (256 KB) at reset. These memory cycles cause the CS5530A to claim the cycle, and generate an ISA bus memory cycle with KBROMCS# asserted. The CS5530A can also be configured to respond to memory addresses FF000000h-FFFFFFFFh (16 MB) and 000E0000h-000FFFFFh (128 KB). Flash ROM is supported in the CS5530A by enabling the KBROMCS# signal on write accesses to the ROM region. Normally only read cycles are passed to the ISA bus, and the KBROMCS# signal is suppressed. When the ROM Write Enable bit (F0 Index 52h[1]) is set, a write access to the ROM address region causes an 8-bit write cycle to occur with MEMW# and KBROMCS# asserted. Table 3-39 shows the ROM interface related programming bits. 3.5.4 Megacells The CS5530A core logic integrates: * Two 8237-equivalent DMA controllers (DMAC) with full 32-bit addressing for DMA transfers. * Two 8259-equivalent interrupt controllers providing 13 individually programmable external interrupts. * An 8254-equivalent timer for refresh, timer, and speaker logic. * NMI control and generation for PCI system errors and all parity errors. * Support for standard AT keyboard controllers, reset control, and VSA technology audio.
Table 3-39. ROM Interface Related Bits
Bit Description ROM/AT Logic Control Register (R/W) Reset Value = F8h
F0 Index 52h 2
Upper ROM Address Range: KBROMCS# is asserted for ISA memory read accesses. 0 = FFFC0000h-FFFFFFFFh (256 KB, Default); 1 = FF000000h-FFFFFFFFh (16 MB) Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). ROM Write Enable: Assert KBROMCS# during writes to configured ROM space (configured in bits 2 and 0), allowing Flash programming. 0 = Disable; 1 = Enable. Lower ROM Address Range: KBROMCS# is asserted for ISA memory read accesses. 0 = 000F0000h-000FFFFFh (64 KB, Default); 1 = 000E0000h-000FFFFFh (128 KB). Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). Decode Control Register 2 (R/W) Reset Value = 20h
1 0
F0 Index 5Bh 5
BIOS ROM Positive Decode: Selects PCI positive or subtractive decoding for accesses to the configured ROM space. 0 = Subtractive; 1 = Positive. ROM configuration is at F0 Index 52h[2:0].
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Functional Description (Continued)
3.5.4.1 Direct Memory Access (DMA) The 8237-compatible DMA controllers in the CS5530A control transfers between ISA I/O devices and system memory. They generate a bus request to the PCI bus when an I/O device requests a DMA operation. Once they are granted the bus, the DMA transfer cycle occurs. DMA transfers can occur over the entire 32-bit address range of the PCI bus. Software DMA is not supported. The CS5530A contains registers for driving the high address bits (high page) and registers for generating the middle address bits (low page) output by the 8237 controller. DMA Controllers The CS5530A supports seven DMA channels using two standard 8237-equivalent controllers. DMA Controller 1 contains Channels 0 through 3 and supports 8-bit I/O adapters. These channels are used to transfer data between 8-bit peripherals and PCI memory or 8/16-bit ISA memory. Using the high and low page address registers, a full 32-bit PCI address is output for each channel so they can all transfer data throughout the entire 4 GB system address space. Each channel can transfer data in 64 KB pages. DMA Controller 2 contains Channels 4 through 7. Channel 4 is used to cascade DMA Controller 1, so it is not available externally. Channels 5 through 7 support 16-bit I/O adapters to transfer data between 16-bit I/O adapters and 16-bit system memory. Using the high and low page address registers, a full 32-bit PCI address is output for each channel so they can all transfer data throughout the entire 4 GB system address space. Each channel can transfer data in 128 KB pages. Channels 5, 6, and 7 transfer 16-bit WORDs on even byte boundaries only. DMA Transfer Modes Each DMA channel can be programmed for single, block, demand or cascade transfer modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after every cycle. This allows the CS5530A to timeshare the PCI bus with the CPU. This is imperative, especially in cases involving large data transfers, so that the CPU does not get locked out for too long. In block transfer mode, the DMA controller executes all of its transfers consecutively without releasing the PCI bus. In demand transfer mode, DMA transfer cycles continue to occur as long as DRQ is high or terminal count is not reached. In this mode, the DMA controller continues to execute transfer cycles until the I/O device drops DRQ to indicate its inability to continue providing data. For this case, the PCI bus is held by the CS5530A until a break in the transfers occurs. In cascade mode, the channel is connected to another DMA controller or to an ISA bus master, rather than to an I/O device. In the CS5530A, one of the 8237 controllers is designated as the master and the other as the slave. The HOLD output of the slave is tied to the DRQ0 input of the master (Channel 4), and the master's DACK0# output is tied to the slave's HLDA input. In each of these modes, the DMA controller can be programmed for read, write, or verify transfers. Both DMA controllers are reset at Power On Reset (POR) to fixed priority. Since master Channel 0 is actually connected to the slave DMA controller, the slave's four DMA channels have the highest priority, with Channel 0 as highest and Channel 3 as the lowest. Immediately following slave Channel 3, master Channel 1 (Channel 5) is the next highest, followed by Channels 6 and 7. DMA Controller Registers The DMA controller can be programmed with standard I/O cycles to the standard register space for DMA. The I/O addresses of all registers for the DMA controller are listed in Table 4-27 "DMA Channel Control Registers" on page 220. Addresses under Master are for the 16-bit DMA channels, and Slave corresponds to the 8-bit channels. When writing to a channel's address or word-count register, the data is written into both the base register and the current register simultaneously. When reading a channel address or word count register, only the current address or word count can be read. The base address and base word count are not accessible for reading. DMA Transfer Types Each of the seven DMA channels may be programmed to perform one of three types of transfers: read, write, or verify. The transfer type selected defines the method used to transfer a BYTE or WORD during one DMA bus cycle. For read transfer types, the CS5530A reads data from memory and writes it to the I/O device associated with the DMA channel. For write transfer types, the CS5530A reads data from the I/O device associated with the DMA channel and writes to the memory. The verify transfer type causes the CS5530A to execute DMA transfer bus cycles, including generation of memory addresses, but neither the Read nor Write command lines are activated. This transfer type was used by DMA Channel 0 to implement DRAM refresh in the original IBM PC/XT. DMA Priority The DMA controller may be programmed for two types of priority schemes: fixed and rotate (I/O Ports 008h[4] and 0D0h[4]), as shown in Table 4-27 "DMA Channel Control Registers" on page 220. In fixed priority, the channels are fixed in priority order based on the descending values of their numbers. Thus, Channel 0 has the highest priority. In rotate priority, the last channel to get service becomes the lowest-priority channel with the priority of the others rotating accordingly. This prevents a channel from dominating the system.
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Functional Description (Continued)
The address and word count registers for each channel are 16-bit registers. The value on the data bus is written into the upper byte or lower byte, depending on the state of the internal addressing byte pointer. This pointer can be cleared by the Clear Byte Pointer command. After this command, the first read/write to an address or word count register will read/write to the low byte of the 16-bit register and the byte pointer will point to the high byte. The next read/write to an address or word-count register will read or write to the high byte of the 16-bit register and the byte pointer will point back to the low byte. When programming the 16-bit channels (Channels 5, 6, and 7), the address which is written to the base address register must be the real address divided by two. Also, the base word count for the 16-bit channels is the number of 16-bit WORDs to be transferred, not the number of bytes as is the case for the 8-bit channels. The DMA controller allows the user to program the active level (low or high) of the DRQ and DACK# signals. Since the two controllers are cascaded together internally on the chip, these signals should always be programmed with the DRQ signal active high and the DACK# signal active low. DMA Shadow Registers The CS5530A contains a shadow register located at F0 Index B8h (Table 3-40) for reading the configuration of the DMA controllers. This read-only register can sequence to read through all of the DMA registers. DMA Addressing Capability DMA transfers occur over the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA controller's 16-bit memory address registers in conjunction with an 8-bit DMA Low Page register and an 8-bit DMA High Page register. These registers, associated with each channel, provide the 32-bit memory address capability. A write to the Low Page register clears the High Page register, for backward compatibility with the PC/AT standard. The starting address for the DMA transfer must be programmed into the DMA controller registers and the channel's respective Low and High Page registers prior to beginning the DMA transfer. DMA Page Registers and Extended Addressing The DMA Page registers provide the upper address bits during DMA cycles. DMA addresses do not increment or decrement across page boundaries. Page boundaries for the 8-bit channels (Channels 0 through 3) are every 64 KB and page boundaries for the 16-bit channels (Channels 5, 6, and 7) are every 128 KB. Before any DMA operations are performed, the Page Registers must be written at the I/O Port addresses shown in Table 4-28 "DMA Page Registers" on page 223 to select the correct page for each DMA channel. The other address locations between 080h and 08Fh and 480h and 48Fh are not used by the DMA channels, but can be read or written by a PCI bus master. These registers are reset to zero at POR. A write to the Low Page register clears the High Page register, for backward compatibility with the PC/AT standard. For most DMA transfers, the High Page register is set to zeros and is driven onto PCI address bits AD[31:24] during DMA cycles. This mode is backward compatible with the PC/AT standard. For DMA extended transfers, the High Page register is programmed and the values are driven onto the PCI addresses AD[31:24] during DMA cycles to allow access to the full 4 GB PCI address space. DMA Address Generation The DMA addresses are formed such that there is an upper address, a middle address, and a lower address portion. The upper address portion, which selects a specific page, is generated by the Page registers. The Page registers for each channel must be set up by the system before a DMA operation. The DMA Page register values are driven on PCI address bits AD[31:16] for 8-bit channels and AD[31:17] for 16-bit channels.
Table 3-40. DMA Shadow Register
Bit Description DMA Shadow Register (RO) Reset Value = xxh
F0 Index B8h 7:0
DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. DMA Channel 0 Mode Register DMA Channel 1 Mode Register DMA Channel 2 Mode Register DMA Channel 3 Mode Register DMA Channel 4 Mode Register DMA Channel 5 Mode Register DMA Channel 6 Mode Register DMA Channel 7 Mode Register DMA Channel Mask Register (bit 0 is channel 0 mask, etc.) DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 ms, all other bits are 0)
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Functional Description (Continued)
The middle address portion, which selects a block within the page, is generated by the DMA controller at the beginning of a DMA operation and any time the DMA address increments or decrements through a block boundary. Block sizes are 256 bytes for 8-bit channels (Channels 0 through 3) and 512 bytes for 16-bit channels (Channels 5, 6, and 7). The middle address bits are driven on PCI address bits AD[15:8] for 8-bit channels and AD[16:9] for 16-bit channels. The lower address portion is generated directly by the DMA controller during DMA operations. The lower address bits are output on PCI address bits AD[7:0] for 8-bit channels and AD[8:1] for 16-bit channels. SBHE# is configured as an output during all DMA operations. It is driven as the inversion of AD0 during 8-bit DMA cycles and forced low for all 16-bit DMA cycles. 3.5.4.2 Programmable Interval Timer The CS5530A contains an 8254-equivalent Programmable Interval Timer (PIT) configured as shown in Figure 3-14. The PIT has three timers/counters, each with an input frequency of 1.19318 MHz (OSC divided by 12), and individually programmable to different modes. The gates of Counter 0 and 1 are usually enabled, however, they can be controlled via F0 Index 50h (see Table 341). The gate of Counter 2 is connected to I/O Port 061h[0]. The output of Counter 0 is connected internally to IRQ0. This timer is typically configured in Mode 3 (square wave output), and used to generate IRQ0 at a periodic rate to be used as a system timer function. The output of Counter 1 is connected to I/O Port 061h[4]. The reset state of I/O Port 061h[4] is 0 and every falling edge of Counter 1 output causes I/O Port 061h[4] to flip states. The output of Counter 2 is brought out to the PC_BEEP output. This output is gated with I/O Port 061h[1].
Table 3-41. PIT Control and I/O Port 061h Associated Register Bits
Bit Description PIT Control/ISA CLK Divider (R/W) Reset Value = 7Bh
F0 Index 50h 7 6 5 4 3
PIT Software Reset: 0 = Disable; 1 = Enable. PIT Counter 1: 0 = Forces Counter 1 output (OUT1) to zero; 1 = Allows Counter 1 output (OUT1) to pass to I/O Port 061h[4]. PIT Counter 1 Enable: 0 = Sets GATE1 input low; 1 = Sets GATE1 input high. PIT Counter 0: 0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0. PIT Counter 0 Enable: 0 = Sets GATE0 input low; 1 = Sets GATE0 input high. Port B Control Register (R/W) Reset Value = 00x01100b
I/O Port 061h 5 4 1 0
PIT OUT2 State (Read Only): This bit reflects the current status of the PIT Counter 2 (OUT2). Toggle (Read Only): This bit toggles on every falling edge of Counter 1 (OUT1). PIT Counter2 (SPKR): 0 = Forces Counter 2 output (OUT2) to zero; 1 = Allows Counter 2 output (OUT2) to pass to the speaker. PIT Counter2 Enable: 0 = Sets GATE2 input low; 1 = Sets GATE2 input high.
CLK0 1.19318 MHz CLK1 CLK2 F0 Index 50h[3] F0 Index 50h[5] I/O Port 061h[0] A[1:0] XD[7:0] IOW# IOR# WR# RD# GATE0 GATE1 GATE2
OUT0
IRQ0 F0 Index 50h[4]
OUT1
I/O Port 061h[4] F0 Index 50h[6]
OUT2
PC_BEEP I/O Port 061h[1]
Figure 3-14. PIT Timer
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Functional Description (Continued)
PIT Registers The PIT registers are summarized and bit formats are in Table 4-29 "Programmable Interval Timer Registers" on page 224. PIT Shadow Register The PIT registers are shadowed to allow for Save-toDisk/RAM to save/restore the PIT state by reading the PIT's counter and write-only registers. The read sequence for the shadow register is listed in F0 Index BAh, Table 342. 3.5.4.3 Programmable Interrupt Controller The CS5530A includes an AT-compatible Programmable Interrupt Controller (PIC) configuration with two 8259equivalent interrupt controllers in a master/slave configuration (Figure 3-15). These PIC devices support all x86 modes of operation except Special Fully Nested Mode.
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
8254 Timer 0
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
INTR
RTC_IRQ#
Coprocessor
IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
INTR
Figure 3-15. PIC Interrupt Controllers
Table 3-42. PIT Shadow Register
Bit Description PIT Shadow Register (RO) Reset Value = xxh
F0 Index BAh 7:0
PIT Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interval Timer registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. Counter 0 LSB (least significant byte) 2. Counter 0 MSB 3. Counter 1 LSB 4. Counter 1 MSB 5. Counter 2 LSB 6. Counter 2 MSB 7. Counter 0 Command Word 8. Counter 1 Command Word 9. Counter 2 Command Word Note: The LSB/MSB of the count is the Counter base value, not the current value. Bits [7:6] of the command words are not used.
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Of the 16 IRQs, four are mapped as shown in Table 3-43, leaving 12 external interrupts. The two controllers are cascaded through IRQ2. The internal 8254 PIT connects to IRQ0. The real-time clock interface chip (see Figure 3-18 "External RTC Interface" on page 107) and the external coprocessor interface (see Figure 3-1 "Processor Signal Connections" on page 42) connect to IRQ8# and IRQ13 respectively. CPU. The interrupt controller then responds to the interrupt acknowledge (INTA) cycles from the CPU. On the first INTA cycle the cascading priority is resolved to determine which of the two 8259 controllers output the interrupt vector onto the data bus. On the second INTA cycle the appropriate 8259 controller drives the data bus with the correct interrupt vector for the highest priority interrupt. By default, the CS5530A responds to PCI INTA cycles because the system interrupt controller is located within the CS5530A. This may be disabled with F0 Index 40h[7] (see Table 3-44). When the CS5530A responds to a PCI INTA cycle, it holds the PCI bus and internally generates the two INTA cycles to obtain the correct interrupt vector. It then asserts TRDY# and returns the interrupt vector. PIC I/O Registers Each PIC contains registers located in the standard I/O address locations, as shown in Table 4-30 "Programmable Interrupt Controller Registers" on page 225. An initialization sequence must be followed to program the interrupt controllers. The sequence is started by writing Initialization Command Word 1 (ICW1). After ICW1 has been written, the controller expects the next writes to follow in the sequence ICW2, ICW3, and ICW4 if it is needed. The Operation Control Words (OCW) can be written after initialization. The PIC must be programmed before operation begins. Since the controllers are operating in cascade mode, ICW3 of the master controller should be programmed with a value indicating that IRQ2 input of the master interrupt controller is connected to the slave interrupt controller rather than an I/O device as part of the system initialization code. In addition, ICW3 of the slave interrupt controller should be programmed with the value 02h (slave ID) and corresponds to the input on the master controller.
Table 3-43. PIC Interrupt Mapping
Master IRQ# IRQ0 IRQ2 IRQ8# IRQ13 IRQ[15:14, 12:9, 7:3, 1] Mapping Connected to the OUT0 (system timer) of the internal 8254 PIT. Connected to the slave's INTR for a cascaded configuration. Connected to external real-time clock. Connected to the coprocessor interface. External interrupts.
The CS5530A allows the PCI interrupt signals INTA#INTD# (also known in industry terms as PIRQx#) to be routed internally to any IRQ signal. The routing can be modified through the CS5530A's configuration registers. If this is done, the IRQ input must be configured to be levelrather than edge-sensitive. IRQ inputs may be individually programmed to be active low, level-sensitive with the Interrupt Sensitivity configuration registers at I/O address space 4D0h and 4D1h. PCI interrupt configuration is discussed in further detail in Section 3.5.4.4 "PCI Compatible Interrupts" on page 101. PIC Interrupt Sequence A typical AT-compatible interrupt sequence is as follows. Any unmasked interrupt generates the INTR signal to the
Table 3-44. PCI INTA Cycle Disable/Enable Bit
Bit Description PCI Function Control Register 1 (R/W) Reset Value = 89h
F0 Index 40h 7
PCI Interrupt Acknowledge Cycle Response: Allow the CS5530A responds to PCI interrupt acknowledge cycles. 0 = Disable; 1 = Enable.
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PIC Shadow Register The PIC registers are shadowed to allow for Save-toDisk/RAM to save/restore the PIC state by reading the PIC's write-only registers. A write to this register resets the read sequence to the first register. The read sequence for the shadow register is listed in F0 Index B9h (Table 3-45).
Table 3-45. PIC Shadow Register
Bit Description PIC Shadow Register (RO) Reset Value = xxh
F0 Index B9h 7:0
PIC Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interrupt Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. PIC1 ICW1 PIC1 ICW2 PIC1 ICW3 PIC1 ICW4 - Bits [7:5] of ICW4 are always 0 PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1 PIC2 ICW1 PIC2 ICW2 PIC2 ICW3 PIC2 ICW4 - Bits [7:5] of ICW4 are always 0 PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1
Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register value, then with the shadow register value ORed with C0h.
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3.5.4.4 PCI Compatible Interrupts The CS5530A allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also known in industry terms as PIRQx#) to be mapped internally to any IRQ signal with the PCI Interrupt Steering Registers 1 and 2, F0 Index 5Ch and 5Dh (Table 3-46). This reassignment does not disable the corresponding IRQ pin. Two interrupt signals may not be assigned to the same IRQ. PCI interrupts are low-level sensitive, whereas PC/AT interrupts are positive-edge sensitive; therefore, the PCI interrupts are inverted before being connected to the 8259. Although the controllers default to the PC/AT-compatible mode (positive-edge sensitive), each IRQ may be individually programmed to be edge or level sensitive using the Interrupt Edge/Level Sensitivity registers in I/O Port 4D0h and 4D1h, as shown in Table 3-47. However, if the controllers are programmed to be level-sensitive via ICW1, all interrupts must be level-sensitive. Figure 3-16 shows the PCI interrupt mapping for the master/slave 8259 interrupt controller.
IRQ[13,8,0] 3 12 ICW1 16 IRQ3 IRQ4 MASTER/SLAVE 8259 PIC IRQ15 1 IRQ[15:14,12:9,7:3,1] PCI INTA#-INTD#
Steering Registers F0 Index 5Ch,5Dh 12 4
Level/Edge Sensitivity 4D0h/4D1h
INTR
Figure 3-16. PCI and IRQ Interrupt Mapping
Table 3-46. PCI Interrupt Steering Registers
Bit Description PCI Interrupt Steering Register 1 (R/W) 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 ` Reset Value = 00h 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15
F0 Index 5Ch 7:4 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 3:0 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3
INTB# Target Interrupt: Selects target interrupt for INTB#.
INTA# Target Interrupt: Selects target interrupt for INTA#.
Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. F0 Index 5Dh 7:4 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 3:0 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 PCI Interrupt Steering Register 2 (R/W) 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 Reset Value = 00h 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15
INTD# Target Interrupt: Selects target interrupt for INTD#.
INTC# Target Interrupt: Selects target interrupt for INTC#.
Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility.
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Table 3-47. Interrupt Edge/Level Select Registers
Bit Description Interrupt Edge/Level Select Register 1 (R/W) Reset Value = 00h
I/O Port 4D0h 7 6 5 4 3 2 1 0
IRQ7 Edge or Level Select: Selects PIC IRQ7 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ6 Edge or Level Select: Selects PIC IRQ6 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ5 Edge or Level Select: Selects PIC IRQ5 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ4 Edge or Level Select: Selects PIC IRQ4 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ3 Edge or Level Select: Selects PIC IRQ3 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0. IRQ1 Edge or Level Select: Selects PIC IRQ1 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0.
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 4D1h 7 6 5 4 3 2 1 0 Interrupt Edge/Level Select Register 2 (R/W) Reset Value = 00h
IRQ15 Edge or Level Select: Selects PIC IRQ15 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ14 Edge or Level Select: Selects PIC IRQ14 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0. IRQ12 Edge or Level Select: Selects PIC IRQ12 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ11 Edge or Level Select: Selects PIC IRQ11 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ10 Edge or Level Select: Selects PIC IRQ10 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ9 Edge or Level Select: Selects PIC IRQ9 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0.
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).
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3.5.5 I/O Ports 092h and 061h System Control The CS5530A supports control functions of I/O Ports 092h (Port A) and 061h (Port B) for PS/2 compatibility. I/O Port 092h allows a fast assertion of the A20M# or CPU_RST. I/O Port 061h controls NMI generation and reports system status. Table 3-48 shows these register bit formats. The CS5530A does not use a pin to control A20 Mask when used together with a GX-series processor. Instead, it generates an SMI for every internal change of the A20M# state and the SMI handler sets the A20M# state inside the CPU. This method is used for both the Port 092h (PS/2) and Port 061h (keyboard) methods of controlling A20M#.
Table 3-48. I/O Ports 061h and 092h
Bit Description Port B Control Register (R/W) Reset Value = 00x01100b
I/O Port 061h 7
PERR#/SERR# Status (Read Only): Was a PCI bus error (PERR#/SERR#) asserted by a PCI device or by the CS5530A? 0 = No; 1 = Yes. This bit can only be set if ERR_EN (bit 2) is set 0. This bit is set 0 after a write to ERR_EN with a 1 or after reset. IOCHK# Status (Read Only): Is an I/O device reporting an error to the CS5530A? 0 = No; 1 = Yes. This bit can only be set if IOCHK_EN (bit 3) is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset. PIT OUT2 State (Read Only): This bit reflects the current status of the PIT Counter 2 (OUT2). Toggle (Read Only): This bit toggles on every falling edge of Counter 1 (OUT1). IOCHK Enable: 0 = Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control. 1 = Ignores the IOCHK# input signal and does not generate NMI.
6 5 4 3
2 1 0
PERR#/SERR# Enable: Generates an NMI if PERR#/SERR# is driven active to report an error. 0 = Enable; 1 = Disable PIT Counter2 (SPKR): 0 = Forces Counter 2 output (OUT2) to zero; 1 = Allows Counter 2 output (OUT2) to pass to the speaker. PIT Counter2 Enable: 0 = Sets GATE2 input low; 1 = Sets GATE2 input high. Port A Control Register (R/W) Reset Value = 02h
I/O Port 092h 7:2 1 0 Reserved: Set to 0.
A20M# SMI Assertion: Assert A20M#. 0 = Enable mask; 1 = Disable mask. Fast CPU Reset: WM_RST SMI is asserted to the BIOS. 0 = Disable; 1 = Enable. This bit must be cleared before the generation of another reset.
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3.5.5.1 I/O Port 092h System Control I/O Port 092h allows for a fast keyboard assertion of an A20# SMI and a fast keyboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3] (Table 3-49). The assertion of a fast keyboard A20# SMI is controlled by either I/O Port 092h or by monitoring for the keyboard command sequence (see Section 3.5.6.1 "Fast Keyboard Gate Address 20 and CPU Reset" on page 106). If bit 1 of I/O Port 092h is cleared, the CS5530A internally asserts an A20M# SMI, which in turn causes an SMI to the processor. If bit 1 is set, A20M# SMI is internally deasserted again causing an SMI. The assertion of a fast keyboard reset (WM_RST SMI) is controlled by bit 0 in I/O Port 092h or by monitoring for the keyboard command sequence. If bit 0 is changed from a 0 to a 1, the CS5530A generates a reset to the processor by generating a WM_RST SMI. When the WM_RST SMI occurs, the BIOS jumps to the Warm Reset vector. This bit remains set until the CS5530A is externally reset, or this bit is cleared by program control. Note that Warm Reset is not a pin; it is under SMI control. 3.5.5.2 I/O Port 061h System Control Through I/O Port 061h, the speaker output can be enabled, NMI from IOCHK# or SERR# can be enabled, the status of IOCHK# and SERR# can be read, and the state of the speaker data (Timer2 output) and refresh toggle (Timer1 output) can be read back. Note that NMI is under SMI control. Even though the hardware is present, the IOCHK# pin does not exist so an NMI from IOCHK# can not happen. 3.5.5.3 SMI Generation for NMI Figure 3-17 shows how the CS5530A can generate an SMI for an NMI. Note that NMI is not a pin.
Table 3-49. I/O Port 092h Decode Enable Bit
Bit Description ROM/AT Logic Control Register (R/W) Reset Value = F8h
F0 Index 52h 3
Enable I/O Port 092h Decode (Port A): I/O Port 092h decode and the logical functions. 0 = Disable; 1 = Enable.
Parity Errors AND
F0 Index 04h[6] F0 Index 41h[5] AND
System Errors AND OR
F0 Index 04h[8]
IOCHK# AND
I/O Port 061h[3]
SERR# I/O Port 061h[2]
NMI
PERR# F0 Index 04h: PCI Command Register Bit 6 = PE (Parity Error Enable) Bit 8 = SERR# (SERR# Enable) F0 Index 41h: PCI Function Control Register 2 Bit 5 = PES (PERR# Signals SERR#) I/O Port 061h: Port B Bit 2 = ERR_EN (PERR#/SERR# enable) Bit 3 = IOCHK_EN (IOCHK Enable) I/O Port 070h: RTC Index Register (WO) Bit 7 = NMI (NMI Enable) AND NMI OR I/O Port 070h[7] AND SMI
Figure 3-17. SMI Generation for NMI
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3.5.6 Keyboard Interface Function The CS5530A actively decodes the keyboard controller I/O Ports 060h and 064h, and generate an ISA I/O cycle with KBROMCS# asserted. Access to I/O Ports 062h and 066h must be enabled for KBROMCS# to be asserted. The CS5530A also actively decodes the keyboard controller I/O Ports 062h and 066h if F0 Index 5Bh[7] is set. Keyboard positive decoding can be disabled if F0 Index 5Ah[1] is cleared. Table 3-50 shows these two decoding bits. Table 3-51 lists the standard keyboard control I/O registers and their bit formats. .
Table 3-50. Decode Control Registers
Bit Description Decode Control Register 1 (R/W) Reset Value = 03h
F0 Index 5Ah 1
Keyboard Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 060h and 064h (and 062h/066h if enabled). 0 = Subtractive; 1 = Positive.
Note: Positive decoding by the CS5530A speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530A. It is assumed that if positive decode is enabled, the port exists on the ISA bus. F0 Index 5Bh 7 Decode Control Register 2 (R/W) Reset Value = 20h
Keyboard I/O Port 062h/066h Decode: This alternate port to the keyboard controller is provided in support of the 8051SL notebook keyboard controller mailbox. 0 = Disable; 1 = Enable.
Note: Positive decoding by the CS5530A speeds up the I/O cycle time. The keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in the CS5530A. It is assumed that if positive decode is enabled, the port exists on the ISA bus.
Table 3-51. External Keyboard Controller Registers
Bit Description External Keyboard Controller Data Register
I/O Port 060h (R/W)
Keyboard Controller Data Register: All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 062h (R/W) External Keyboard Controller Mailbox Register
Keyboard Controller Mailbox Register: Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]). I/O Port 064h (R/W) External Keyboard Controller Command Register
Keyboard Controller Command Register: All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 066h (R/W) External Keyboard Controller Mailbox Register
Keyboard Controller Mailbox Register: Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]).
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Fast Keyboard Gate Address 20 and CPU Reset The CS5530A monitors the keyboard I/O Ports 064h and 060h for the fast keyboard A20M# and CPU reset control sequences. If a write to I/O Port 060h[1] = 1 after a write takes place to I/O Port 064h with data of D1h, then the CS5530A asserts the A20M# signal. A20M# remains asserted until cleared by: (1) a write to bit 1 of I/O Port 092h, (2) a CPU reset of some kind, or (3) write to I/O Port 060h[1] = 0 after a write takes place to I/O Port 064h with data of D1h. 3.5.6.1 The CS5530A also monitors the keyboard ports for the CPU reset control sequence. If a write to I/O Port 060h with data bit 0 set occurs after a write to I/O Port 064h with data of D1h, the CS5530A asserts a WM_RST SMI. The fast keyboard A20M# and CPU reset can be disabled through F0 Index 52h[7]. By default, bit 7 is cleared, and the fast keyboard A20M# and CPU reset monitor logic is active. If bit 7 is clear, the CS5530A forwards the commands to the keyboard controller. By default, the CS5530A forces the deassertion of A20M# during a warm reset. This action may be disabled if F0 Index 52h[4] is cleared.
Table 3-52. A20 Associated Programming Bits
Bit Description ROM/AT Logic Control Register (R/W) Reset Value = F8h
F0 Index 52h 7
Snoop Fast Keyboard Gate A20 and Fast Reset: Enables the snoop logic associated with keyboard commands for A20 Mask and Reset. 0 = Disable; 1 = Enable (snooping). If disabled, the keyboard controller handles the commands. Enable A20M# Deassertion on Warm Reset: Force A20M# high during a Warm Reset (guarantees that A20M# is deasserted regardless of the state of A20). 0 = Disable; 1 = Enable.
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3.5.7 External Real-Time Clock Interface I/O Ports 070h and 071h decodes are provided to interface to an external real-time clock controller. I/O Port 070h, a write only port, is used to set up the address of the desired data in the controller. This causes the address to be placed on the ISA data bus, and the RTCALE signal to be triggered. A read of I/O Port 071h causes an ISA I/O read cycle to be performed while asserting the RTCCS# signal. A write to I/O Port 071h causes an ISA I/O write cycle to be performed with the desired data being placed on the ISA bus and the RTCCS# signal to be asserted. RTCCS#/ SMEMW# and RTCALE/SMEMR# are multiplexed pins. The function selection is made through F0 Index 53h[2]. The connection between the CS5530A and an external real-time clock is shown in Figure 3-18. The CS5530A also provides the RTC Index Shadow Register (F0 Index BBh) to store the last write to I/O Port 070h. Table 3-53 shows the bit formats for the associated registers for interfacing with an external real-time clock.
SD[7:0] IOW# IOR# RTCCS#/SMEMW# RTCALE/SMEMR# RTC IRQ8#
Figure 3-18. External RTC Interface
Table 3-53. Real-Time Clock Registers
Bit Description RTC Address Register
I/O Port 070h (WO) 7 6:0 NMI Mask: 0 = Enable; 1 = Mask.
RTC Register Index: A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
Note: This register is shadowed within the CS5530A and is read through the RTC Shadow Register (F0 Index BBh). I/O Port 071h (R/W) RTC Data Register
A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#. A write of this register sets the value into the register indexed by the RTC Address Register plus initiates a RTCCS#. F0 Index BBh 7:0 RTC Index Shadow Register (RO) Reset Value = xxh
RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index register (I/O Port 070h). Alternate CPU Support Register (R/W) Reset Value = 00h
F0 Index 53h 2
RTC Enable/RTC Pin Configuration: 0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled; 1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled. Note: The RTC Index Shadow Register (F0 Index BBh) is independent of the setting of this bit.
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3.6 IDE CONTROLLER
be independently programmed allowing high-speed IDE peripherals to coexist on the same channel as older, compatible devices. The CS5530A also provides a software-accessible buffered reset signal to the IDE drive, F0 Index 44h[3:2] (Table 354). The IDE_RST# signal is driven low during reset to the CS5530A and can be driven low or high as needed for device-power-off conditions. 3.6.1 IDE Interface Signals The CS5530A has two completely separate IDE control signals, however, the IDE_RST#, IDE_ADDR[2:0] and IDE_DATA[15:0] are shared. The connections between the CS5530A and IDE devices are shown as Figure 3-19. The CS5530A integrates a fully-buffered, 32-bit, ANSI ATA4-compliant (Ultra DMA33) IDE interface. The IDE interface supports two channels, primary and secondary, each supporting two devices that can operate in PIO Modes 1, 2, 3, 4, Multiword DMA, or Ultra DMA/133. The IDE interface provides a variety of features to optimize system performance, including 32-bit disk access, post write buffers, bus master, Multiword DMA, look-ahead read buffer, and prefetch mechanism for each channel respectively. The IDE interface timing is completely programmable. Timing control covers the command active and recover pulse widths, and command block register accesses. The IDE data-transfer speed for each device on each channel can
Table 3-54. IDE Reset Bits
Bit Description Reset Control Register (R/W) Reset Value = xx000000b
F0 Index 44h 3 2
IDE Controller Reset: Reset both of the CS5530A IDE controllers' internal state machines. 0 = Run; 1 = Reset. This bit is level-sensitive and must be explicitly cleared to 0 to remove the reset. IDE Reset: Reset IDE bus. 0 = Deassert IDE bus reset signal; 1 = Assert IDE bus reset signal. This bit is level-sensitive and must be explicitly cleared to 0 to remove the reset.
IDE_DATA[15:0] IDE_ADDR[2:0] IDE_CS0#, IDE_DREQ0, IDE_DACK0#, IDE_IORDY0, IDE_IOR0#, IDE_IOW0# IDE_RST# Primary Channel IRQ14
IDE_CS1#, IDE_DREQ1, IDE_DACK1#, IDE_IORDY1, IDE_IOR1#, IDE_IOW1#
Secondary Channel
IRQ15
Figure 3-19. CS5530A and IDE Channel Connections
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3.6.2 IDE Configuration Registers Registers for configuring the IDE interface are accessed through F2 Index 20h, the Base Address Register (F2BAR) in Function 2. F2BAR sets the base address for the IDE Controllers Configuration Registers as shown in Table 355. For complete bit information, refer to Section 4.3.3 "IDE Controller Registers - Function 2" on page 188. The following subsections discuss CS5530A operational/programming details concerning PIO, Bus Master, and Ultra DMA/33 modes. 3.6.2.1 PIO Mode The IDE data port transaction latency consists of address latency, asserted latency and recovery latency. Address latency occurs when a PCI master cycle targeting the IDE data port is decoded, and the IDE_ADDR[2:0] and IDE_CS# lines are not set up. Address latency provides the setup time for the IDE_ADDR[2:0] and IDE_CS# lines prior to IDE_IOR# and IDE_IOW#. Asserted latency consists of the I/O command strobe assertion length and recovery time. Recovery time is provided so that transactions may occur back-to-back on the IDE interface without violating minimum cycle periods for the IDE interface. If IDE_IORDY is asserted when the initial sample point is reached, no wait states are added to the command strobe assertion length. If IDE_IORDY is negated when the initial sample point is reached, additional wait states are added. Recovery latency occurs after the IDE data port transactions have completed. It provides hold time on the IDE_ADDR[2:0] and IDE_CS# lines with respect to the read and write strobes (IDE_IOR# and IDE_IOW#). The PIO portion of the IDE registers is enabled through: * Channel 0 Drive 0 Programmed I/O Register (F2BAR+I/O Offset 20h) * Channel 0 Drive 1 Programmed I/O Register (F2BAR+I/O Offset 28h) * Channel 1 Drive 0 Programmed I/O Register (F2BAR+I/O Offset 30h) * Channel 1 Drive 1 Programmed I/O Register (F2BAR+I/O Offset 38h) The IDE channels and devices can be individually programmed to select the proper address setup time, asserted time, and recovery time. The bit formats for these registers are shown in Table 3-56. Note that there are different bit formats for each of the PIO programming registers depending on the operating format selected: Format 0 or Format 1. F2BAR+I/O Offset 24h[31] (Channel 0 Drive 0 -- DMA Control Register) sets the format of the PIO register. If bit 31 = 0, Format 0 is used and it selects the slowest PIOMODE (bits [19:16]) per channel for commands. If bit 31 = 1, Format 1 is used and it allows independent control of command and data. Also listed in the bit formats are recommended values for the different PIO modes. Note: These are only recommended settings and are not 100% tested.
Table 3-55. Base Address Register (F2BAR) for IDE Support Registers
Bit Description Base Address Register - F2BAR (R/W) Reset Value = 00000001h
F2 Index 20h-23h
This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [6:0] are read only (0000 001), indicating a 128-byte I/O address range. Refer to Table 4-19 for the IDE configuration registers bit formats and reset values. 31:7 6:0 Bus Mastering IDE Base Address Address Range (Read Only)
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Table 3-56. PIO Programming Registers
Bit Description Channel 0 Drive 0 PIO Register (R/W) Reset Value = 0000E132h (Note)
F2BAR+I/O Offset 20h-23h
If Offset 24h[31] = 0, Format 0: Selects slowest PIOMODE per channel for commands. Format 0 settings for: PIO Mode 0 = 00009172h PIO Mode 1 = 00012171h PIO Mode 2 = 00020080h PIO Mode 3 = 00032010h PIO Mode 4 = 00040010h 31:20 19:16 15:12 11:8 7:4 3:0 Reserved: Set to 0. PIOMODE: PIO mode t2I: Recovery time (value + 1 cycle) t3: IDE_IOW# data setup time (value + 1 cycle) t2W: IDE_IOW# width minus t3 (value + 1 cycle) t1: Address Setup Time (value + 1 cycle)
If Offset 24h[31] = 1, Format 1: Allows independent control of command and data. Format 1 settings for: PIO Mode 0 = 9172D132h PIO Mode 1 = 21717121h PIO Mode 2 = 00803020h PIO Mode 3 = 20102010h PIO Mode 4 = 00100010h 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 t2IC: Command cycle recovery time (value + 1 cycle) t3C: Command cycle IDE_IOW# data setup (value + 1 cycle) t2WC: Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) t1C: Command cycle address setup time (value + 1 cycle) t2ID: Data cycle recovery time (value + 1 cycle) t3D: Data cycle IDE_IOW# data setup (value + 1 cycle) t2WD: Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) t1D: Data cycle address Setup Time (value + 1 cycle)
Note: The reset value of this register is not a valid PIO Mode. Offset 28h-2Bh Channel 0 Drive 1 PIO Register (R/W) Reset Value = 0000E132h
Channel 0 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 30h-33h Channel 1 Drive 0 PIO Register (R/W) Reset Value = 0000E132h
Channel 1 Drive 0 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 38h-3Bh Channel 1 Drive 1 PIO Register (R/W) Reset Value = 0000E132h
Channel 1 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.
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3.6.2.2 Bus Master Mode Two IDE bus masters are provided to perform the data transfers for the primary and secondary channels. The CS5530A off-loads the CPU and improves system performance in multitasking environments. The bus master mode programming interface is an extension of the standard IDE programming model. This means that devices can always be dealt with using the standard IDE programming model, with the master mode functionality used when the appropriate driver and devices are present. Master operation is designed to work with any IDE device that supports DMA transfers on the IDE bus. Devices that work in PIO mode can only use the standard IDE programming model. The IDE bus masters use a simple scatter/gather mechanism allowing large transfer blocks to be scattered to or gathered from memory. This cuts down on the number of interrupts to and interactions with the CPU. Physical Region Descriptor Table Address Before the controller starts a master transfer it is given a pointer (shown in Table 3-57) to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). The PRDs describe the areas of memory that are used in the data transfer. The PRDs must be aligned on a 4-byte boundary and the table cannot cross a 64 KB boundary in memory. Primary and Secondary IDE Bus Master Registers The IDE Bus Master Registers for each channel (primary and secondary) have an IDE Bus Master Command Register and Bus Master Status Register. These registers must be accessed individually; a 32-bit DWORD access attempting to include both the Command and Status registers may not operate correctly. Bit formats of these registers are given in Table 3-58.
Table 3-57. IDE Bus Master PRD Table Address Registers
Bit Description IDE Bus Master 0 PRD Table Address -- Primary (R/W) Reset Value = 00000000h
F2BAR+I/O Offset 04h-07h 31:2
Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 0. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD.
1:0
Reserved: Set to 0. IDE Bus Master 1 PRD Table Address -- Secondary (R/W) Reset Value = 00000000h
F2BAR+I/O Offset 0Ch-0Fh 31:2
Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 1. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD.
1:0
Reserved: Set to 0.
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Table 3-58. IDE Bus Master Command and Status Registers
Bit Description IDE Bus Master 0 Command Register -- Primary (R/W) Reset Value = 00h
F2BAR+I/O Offset 00h 7:4 3 2:1 0
Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Sets the direction of bus master transfers. 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the bus master. 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 to 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is discarded. This bit should be reset after completion of data transfer.
F2BAR+I/O Offset 02h 7 6 5 4:3 2 1 0
IDE Bus Master 0 Status Register -- Primary (R/W)
Reset Value = 00h
Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes; 1 = No (simplex mode). Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Reserved: Set to 0. Must return 0 on reads. Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes. IDE Bus Master 0 PRD Table Address -- Primary (R/W) Reset Value = 00000000h
F2BAR+I/O Offset 04h-07h 31:2
Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 0. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD.
1:0
Reserved: Set to 0. IDE Bus Master 1 Command Register -- Secondary (R/W) Reset Value = 00h
F2BAR+I/O Offset 08h 7:4 3 2:1 0
Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Sets the direction of bus master transfers. 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the bus master. 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 = 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is discarded. This bit should be reset after completion of data transfer.
F2BAR+I/O Offset 0Ah 7 6 5 4:3 2 1 0
IDE Bus Master 1 Status Register -- Secondary (R/W)
Reset Value = 00h
Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes; 1 = No (simplex mode). Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Reserved: Set to 0. Must return 0 on reads. Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes.
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Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illustrated in Table 3-59. When the bus master is enabled (Command Register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus master does not cache PRDs. The PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be transferred. This pointer must be 16-byte aligned. The second DWORD contains the size (16 bits) of the buffer and the EOT flag. The size must be in multiples of 16 bytes. The EOT bit (bit 31) must be set to indicate the last PRD in the PRD table. Programming Model The following steps explain how to initiate and maintain a bus master transfer between memory and an IDE device. 1) Software creates a PRD table in system memory. Each PRD entry is 8 bytes long, consisting of a base address pointer and buffer size. The maximum data that can be transferred from a PRD entry is 64 KB. A PRD table must be aligned on a 4-byte boundary. The last PRD in a PRD table must have the EOT bit set. Software loads the starting address of the PRD table by programming the PRD Table Address Register. 3) 4) 5) 6) 7) Software must fill the buffers pointed to by the PRDs with IDE data. Write 1 to the Bus Master Interrupt bit and Bus Master Error (Status Register bits 2 and 1) to clear the bits. Set the correct direction to the Read or Write Control bit (Command Register bit 3). Engage the bus master by writing a "1" to the Bus Master Control bit (Command Register bit 0). The bus master reads the PRD entry pointed to by the PRD Table Address Register and increments the address by 08h to point to the next PRD. The transfer begins. The bus master transfers data to/from memory responding to bus master requests from the IDE device. At the completion of each PRD, the bus master's next response depends on the settings of the EOT flag in the PRD. If the EOT bit is set, then the IDE bus master clears the Bus Master Active bit (Status Register bit 0) and stops. If any errors occurred during the transfer, the bus master sets the Bus Master Error bit (Status Register bit 1).
8)
2)
Table 3-59. Physical Region Descriptor Format
Byte 3 Byte 2 Byte 1 8 7 6 5 Byte 0 4 3 0 0 2 0 0 1 0 0 0 0 0
DWORD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 1 E O T Memory Region Physical Base Address [31:4] (IDE Data Buffer) Reserved
Size [15:4]
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3.6.2.3 Ultra DMA/33 Mode The CS5530A supports Ultra DMA/33. It utilizes the standard IDE Bus Master functionality to interface, initiate, and control the transfer. Ultra DMA/33 definition also incorporates a Cyclic Redundancy Check (CRC) error checking protocol to detect errors. The Ultra DMA/33 protocol requires no extra signal pins on the IDE connector. The CS5530A redefines three standard IDE control signals when in Ultra DMA/33 mode. These definitions are shown in Table 3-60. The data transfer phase continues the burst transfers with the CS5530A and the IDE via providing data, toggling STROBE and DMARDY#. IDE_DATA[15:0] is latched by the receiver on each rising and falling edge of STROBE. The transmitter can pause the burst cycle by holding STROBE high or low, and resume the burst cycle by again toggling STROBE. The receiver can pause the burst cycle by negating DMARDY# and resumes the burst cycle by asserting DMARDY#. The current burst cycle can be terminated by either the transmitter or the receiver. A burst cycle must first be paused as described above before it can be terminated. The CS5530A can then stop the burst cycle by asserting STOP, with the IDE device acknowledging by negating IDE_DREQ. The IDE device stops the burst cycle by negating IDE_DREQ and the CS5530A acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a high level. The CS5530A then puts the result of the CRC calculation onto IDE_DATA[15:0] while deasserting IDE_DACK#. The IDE device latches the CRC value on the rising edge of IDE_DACK#. The CRC value is used for error checking on Ultra DMA/33 transfers. The CRC value is calculated for all data by both the CS5530A and the IDE device during the Ultra DMA/33 burst transfer cycles. This result of the CRC calculation is based on all data transferred with a valid STROBE edge while IDE_DACK# is asserted. At the end of the burst transfer, the CS5530A drives the result of the CRC calculation onto IDE_DATA[15:0] which is then strobed by the deassertion of IDE_DACK#. The IDE device compares the CRC result of the CS5530A to its own and reports an error if there is a mismatch. The timings for Ultra DMA/33 are programmed into the DMA control registers: * Channel 0 Drive 0 DMA Control Register (F2BAR+I/O Offset 24h) * Channel 0 Drive 1 DMA Control Register (F2BAR+I/O Offset 2Ch) * Channel 1 Drive 0 DMA Control Register (F2BAR+I/O Offset 34h) * Channel 1 Drive 1 DMA Control Register (F2BAR+I/O Offset 3Ch) The bit formats for these registers are given in Table 3-61. Note that F2BAR+I/O Offset 24h[20] is used to select either Multiword or Ultra DMA mode. Bit 20 = 0 selects Multiword DMA mode. If bit 20 = 1, then Ultra DMA/33 mode is selected. Once mode selection is made using this bit, the remaining DMA Control Registers also operate in the selected mode. Also listed in the bit formats are recommended values for both Multiword DMA Modes 0-2 and Ultra DMA/33 Modes 0-2. Note: These are only recommended settings and are not 100% tested.
Table 3-60. Ultra DMA/33 Signal Definitions
CS5530A IDE Channel Signal IDE_IOW# IDE_IOR# IDE_IORDY Ultra DMA/33 Read Cycle STOP DMARDY# STROBE Ultra DMA/33 Write Cycle STOP STROBE DMARDY#
All other signals on the IDE connector retain their functional definitions during the Ultra DMA/33 operation. IDE_IOW# is defined as STOP for both read and write transfers to request to stop a transaction. IDE_IOR# is redefined as DMARDY# for transferring data from the IDE device to the CS5530A. It is used by the CS5530A to signal when it is ready to transfer data and to add wait states to the current transaction. IDE_IOR# signal is defined as STROBE for transferring data from the CS5530A to the IDE device. It is the data strobe signal driven by the CS5530A on which data is transferred during each rising and falling edge transition. IDE_IORDY is redefined as STROBE for transferring data from the IDE device to the CS5530A during a read cycle. It is the data strobe signal driven by the IDE device on which data is transferred during each rising and falling edge transition. IDE_IORDY is defined as DMARDY# during a write cycle for transferring data from the CS5530A to the IDE device. It is used by the IDE device to signal when it is ready to transfer data and to add wait states to the current transaction. Ultra DMA/33 data transfer consists of three phases, a startup phase, a data transfer phase and a burst termination phase. The IDE device begins the startup phase by asserting IDE_DREQ. When ready to begin the transfer, the CS5530A asserts IDE_DACK#. When IDE_DACK# is asserted, the CS5530A drives IDE_CS0# and IDE_CS1# asserted, and IDE_ADDR[2:0] low. For write cycles, the CS5530A negates STOP, waits for the IDE device to assert DMARDY#, and then drives the first data WORD and STROBE signal. For read cycles, the CS5530A negates STOP, and asserts DMARDY#. The IDE device then sends the first data WORD and asserts STROBE.
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Table 3-61. MDMA/UDMA Control Registers
Bit Description Channel 0 Drive 0 DMA Control Register (R/W) Reset Value = 00077771h
F2BAR+I/O Offset 24h-27h If bit 20 = 0, Multiword DMA
Settings for: Multiword DMA Mode 0 = 00077771h Multiword DMA Mode 1 = 00012121h Multiword DMA Mode 2 = 00002020h 31 30:21 20 19:16 15:12 11:8 7:4 3:0 PIO Mode Format: 0 = Format 0; 1 = Format 1. Reserved: Set to 0. DMA Operation: 0 = Multiword DMA; 1 = Ultra DMA. tKR: IDE_IOR# recovery time (4-bit) (value + 1 cycle) tDR: IDE_IOR# pulse width (value + 1 cycle) tKW: IDE_IOW# recovery time (4-bit) (value + 1 cycle) tDW: IDE_IOW# pulse width (value + 1 cycle) tM: IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1#
If bit 20 = 1, Ultra DMA Settings for: Ultra DMA Mode 0 = 00921250h Ultra DMA Mode 1 = 00911140h Ultra DMA Mode 2 = 00911030h 31 30:21 20 19:16 15:12 11:8 7:4 3:0 PIO Mode Format: 0 = Format 0; 1 = Format 1. Reserved: Set to 0. DMA Operation: 0 = Multiword DMA, 1 = Ultra DMA. tCRC: CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS) tSS: UDMA out (value + 1 cycle) tCYC: Data setup and cycle time UDMA out (value + 2 cycles) tRP: Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock. tACK: IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle) Channel 0 Drive 1 DMA Control Register (R/W) Reset Value = 00017771h
Offset 2Ch-2Fh
Channel 0 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 34h-37h Channel 1 Drive 0 DMA Control Register (R/W) Reset Value = 00017771h
Channel 1 Drive 0 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 3Ch-3Fh Channel 1 Drive 1 DMA Control Register (R/W) Reset Value = 00017771h
Channel 1 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.
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3.7 XPRESSAUDIO
* Trap accesses for serial input and output at COM2 (I/O Port 2F8h-2FFh) or COM4 (I/O Port 2E8h-2EFh). * Support trapping for low (I/O Port 00h-0Fh) and/or high (I/O Port C0h-DFh) DMA accesses. * Support hardware status register reads in CS5530A, minimizing SMI overhead. * Support is provided for software-generated IRQs on IRQ 2, 3, 5, 7, 10, 11, 12, 13, 14, and 15. Included in the following subsections are details regarding the registers used for configuring the audio interface. The registers are accessed through F3 Index 10h, the Base Address Register (F3BAR) in Function 3. F3BAR sets the base address for XpressAUDIO support registers as shown in Table 3-62. 3.7.1 Subsystem Data Transport Hardware The data transport hardware can be broadly divided into two sections: bus mastering and the codec interface. 3.7.1.1 Audio Bus Masters The CS5530A audio hardware includes six PCI bus masters (three for input and three for output) for transferring digitized audio between memory and the external codec. With these bus master engines, the CS5530A off-loads the CPU and improves system performance. The programming interface defines a simple scatter/gather mechanism allowing large transfer blocks to be scattered to or gathered from memory. This cuts down on the number of interrupts to and interactions with the CPU. Through XpressAUDIO, the CS5530A offers a combined hardware/software support solution to meet industry standard audio requirements. XpressAUDIO uses Virtual System Architecture(R) (VSATM) technology along with additional hardware features to provide the necessary support for industry standard 16-bit stereo synthesis and OPL3 emulation. The hardware portion of XpressAUDIO is for transporting streaming audio data to/from the system memory and an AC97 codec. This hardware includes: * Six (three inbound/three outbound) buffered PCI bus mastering engines that drive specific AC97 interface slots. * Interfaces to AC97 codecs (e.g., National's LM4548) for audio input/output. Additional hardware provides the necessary functionality for VSA technology. This hardware includes the ability to: * Generate an SMI to alert software to update required data. An SMI is generated when either audio buffer is half empty or full. If the buffers become completely empty or full, the Empty bit is asserted. * Generate an SMI on I/O traps. * Trap accesses for sound card compatibility at either I/O Port 220h-22Fh, 240h-24Fh, 260h-26Fh, or 280h-28Fh. * Trap accesses for FM compatibility at I/O Port 388h38Bh. * Trap accesses for MIDI UART interface at I/O Port 300h301h or 330h-331h.
Table 3-62. Base Address Register (F3BAR) for XpressAUDIO Registers
Bit Description Base Address Register - F3BAR (R/W) Reset Value = 00000000h
f3 Index 10h-13h
This register sets the base address of the memory mapped audio interface control register block. This is a 128-byte block of registers used to control the audio FIFO and codec interface, as well as to support SMIs produced by VSA technology. Bits [6:0] are read only (0000 0000), indicating a 128-byte memory address range. Refer to Table 4-21 for the bit formats and reset values of the XpressAUDIO registers. 31:7 6:0 Audio Interface Base Address Address Range (Read Only)
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The six bus masters that directly drive specific slots on the AC97 interface: * Audio Bus Master 0 -- Output to codec -- PCI read -- 32-Bit -- Left and right channels -- Slots 3 and 4 * Audio Bus Master 1 -- Input from codec -- PCI write -- 32-Bit -- Left and right channels -- Slots 3 and 4 * Audio Bus Master 2 -- Output to codec -- PCI read -- 16-Bit -- Slot 5 * Audio Bus Master 3 -- Input from codec -- PCI write -- 16-Bit -- Slot 5 * Audio Bus Master 4 -- Output to codec -- PCI read -- 16-Bit -- Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot) * Audio Bus Master 5 - Input from codec -- PCI write -- 16-Bit -- Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot) Bus Master Audio Configuration Registers The format for the bus master audio configuration registers is similar in that each bus master has a Command Register, an SMI Status Register and a PRD Table Address Register. Programming of the bus masters is generic in many ways, although specific programming is required of bit 3 in the Command Register. This bit selects read or write control and is dependent upon which Audio Bus Master is being programmed. For example, Audio Bus Master 0 is defined as an output only, so bit 3 of Audio Bus Master 0 Command Register (F3BAR+Memory Offset 20h[3]) must always be set to 1.
Table 3-63. Generic Bit Formats for Audio Bus Master Configuration Registers
Bit Description Command Register (R/W) 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master X: 0 = Memory reads performed (output to codec); 1 = Memory writes performed (input from codec). This bit should not be changed when the bus master is active. The setting of this bit is dependent upon the assigned bus master. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master X: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must either be paused or have reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: This register must be read and written as a BYTE. SMI Status Register (RC) 7:2 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP (end of page) before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. Must be R/W as a byte. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. PRD Table Address (R/W) 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master X. When written, this register points to the first entry in a PRD table. Once Audio Bus Master X is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Revision 1.1 Reserved: Set to 0. 117 www.national.com
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Table 3-63 on page 117 explains the generic format for the six audio bus masters. Table 3-64 gives the register locations, reset values and specific programming information of bit 3, Read or Write Control, in the Command Register for the Audio Bus Masters.
Table 3-64. Audio Bus Master Configuration Register Summary
Bit Description
Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. F3BAR+Memory Offset 20h F3BAR+Memory Offset 21h F3BAR+Memory Offset 22h-23h F3BAR+Memory Offset 24h-27h Refer to Table 3-63 on page 117 for bit descriptions. Note: Bit 3 of the Command Register must be set to 0 (memory read) for correct operation. Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. F3BAR+Memory Offset 28h F3BAR+Memory Offset 29h F3BAR+Memory Offset 2Ah-2Bh F3BAR+Memory Offset 2Ch-2Fh Refer to Table 3-63 on page 117 for bit descriptions. Note: Bit 3 of the Command Register must be set to 1 (memory write) for correct operation. Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. F3BAR+Memory Offset 30h F3BAR+Memory Offset 31h F3BAR+Memory Offset 32h-33h F3BAR+Memory Offset 34h-37h Refer to Table 3-63 on page 117 for bit descriptions. Note: Bit 3 of the Command Register must be set to 0 (memory read) for correct operation. Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. F3BAR+Memory Offset 38h F3BAR+Memory Offset 39h F3BAR+Memory Offset 3Ah-3Bh F3BAR+Memory Offset 3Ch-3Fh Refer to Table 3-63 for bit descriptions. Note: Bit 3 of the Command Register must be set to 1 (memory write) for correct operation. Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). F3BAR+Memory Offset 40h F3BAR+Memory Offset 41h F3BAR+Memory Offset 42h-43h F3BAR+Memory Offset 44h-47h Refer to Table 3-63 on page 117 for bit descriptions. Note: Bit 3 of the Command Register must be set to 0 (memory read) for correct operation. Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). F3BAR+Memory Offset 48h F3BAR+Memory Offset 49h F3BAR+Memory Offset 4Ah-4Bh F3BAR+Memory Offset 4Ch-4Fh Refer to Table 3-63 on page 117 for bit descriptions. Note: Bit 3 of the Command Register must be set to 1 (memory write) for correct operation. Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h
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3.7.1.2 Physical Region Descriptor Table Address Before the bus master starts a master transfer it must be programmed with a pointer (PRD Table Address Register) to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). The PRDs describe the areas of memory that are used in the data transfer. The descriptor table entries must be aligned on a 4-byte boundary and the table cannot cross a 64 KB boundary in memory. 3.7.1.3 Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illustrated in Table 3-65. When the bus master is enabled (Command Register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus master does not cache PRDs. The PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be transferred. The second DWORD contains the size (16 bits) of the buffer and flags (EOT, EOP, JMP). The description of the flags are as follows: * EOT bit - If set in a PRD, this bit indicates the last entry in the PRD table (bit 31). The last entry in a PRD table must have either the EOT bit or the JMP bit set. A PRD can not have both the JMP and EOT bits set. * EOP bit - If set in a PRD and the bus master has completed the PRD's transfer, the End of Page bit is set (Status Register bit 0 = 1) and an SMI is generated. If a second EOP is reached due to the completion of another PRD before the End of Page bit is cleared, the Bus Master Error bit is set (Status Register bit 1 = 1) and the bus master pauses. In this paused condition, reading the Status Register clears both the Bus Master Error and the End of Page bits and the bus master continues. * JMP bit - This PRD is special. If set, the Memory Region Physical Base Address is now the target address of the JMP. There is no data transfer with this PRD. This PRD allows the creation of a looping mechanism. If a PRD table is created with the JMP bit set in the last PRD, the PRD table does not need a PRD with the EOT bit set. A PRD can not have both the JMP and EOT bits set.
Table 3-65. Physical Region Descriptor Format
Byte 3 Byte 2 Byte 1 8 7 6 5 Byte 0 4 3 2 1 0 0 0
DWORD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 1 EEJ OOM TPP Memory Region Base Address [31:1] (Audio Data Buffer) Reserved
Size [15:1]
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3.7.1.4 Programming Model The following discussion explains, in steps, how to initiate and maintain a bus master transfer between memory and an audio slave device. In the steps listed below, the reference to "Example" refers to Figure 3-20, PRD Table Example. 1) Software creates a PRD table in system memory. Each PRD entry is 8 bytes long; consisting of a base address pointer and buffer size. The maximum data that can be transferred from a PRD entry is 64 KB. A PRD table must be aligned on a 4-byte boundary. The last PRD in a PRD table must have the EOT or JMP bit set. Example - Assume the data is outbound. There are three PRDs in the example PRD table. The first two PRDs (PRD_1, PRD_2) have only the EOP bit set. The last PRD (PRD_3) has only the JMP bit set. This example creates a PRD loop. 2) Software loads the starting address of the PRD table by programming the PRD Table Address Register. Example - Program the PRD Table Address Register with Address_3. 3) Software must fill the buffers pointed to by the PRDs with audio data. It is not absolutely necessary to fill the buffers; however, the buffer filling process must stay ahead of the buffer emptying. The simplest way to do 4) this is by using the EOP flags to generate an SMI when a PRD is empty. Example - Fill Audio Buffer_1 and Audio Buffer_2. The SMI generated by the EOP from the first PRD allows the software to refill Audio Buffer_1. The second SMI will refill Audio Buffer_2. The third SMI will refill Audio Buffer_1 and so on. Read the SMI Status Register to clear the Bus Master Error and End of Page bits (bits 1 and 0). Set the correct direction to the Read or Write Control bit (Command Register bit 3). Note that the direction of the data transfer of a particular bus master is fixed and therefore the direction bit must be programmed accordingly. It is assumed that the codec has been properly programmed to receive the audio data. Engage the bus master by writing a "1" to the Bus Master Control bit (Command Register bit 0). The bus master reads the PRD entry pointed to by the PRD Table Address Register and increments the address by 08h to point to the next PRD. The transfer begins. Example - The bus master is now properly programmed to transfer Audio Buffer_1 to a specific slot(s) in the AC97 interface.
Address_3 Address_1 EOT = 0 EOP = 1 JMP = 0 Address_2 EOT = 0 EOP = 1 JMP = 0 Address_3 EOT = 0 EOP = 0 JMP = 1 PRD_3 Don't Care PRD_2 Size_2 PRD_1 Size_1
Address_1 Audio Buffer_1
Size_1
Address_2
Audio Buffer_2
Size_2
Figure 3-20. PRD Table Example
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5) The bus master transfers data to/from memory responding to bus master requests from the AC97 interface. At the completion of each PRD, the bus master's next response depends on the settings of the flags in the PRD. Example - At the completion of PRD_1 an SMI is generated because the EOP bit is set while the bus master continues on to PRD_2. The address in the PRD Table Address Register is incremented by 08h and is now pointing to PRD_3. The SMI Status Register is read to clear the End of Page status flag. Since Audio Buffer_1 is now empty, the software can refill it. At the completion of PRD_2 an SMI is generated because the EOP bit is set. The bus master then continues on to PRD_3. The address in the PRD Table Address Register is incremented by 08h. The DMA SMI Status Register is read to clear the End of Page status flag. Since Audio Buffer_2 is now empty, the software can refill it. Audio Buffer_1 has been refilled from the previous SMI. PRD_3 has the JMP bit set. This means the bus master uses the address stored in PRD_3 (Address_3) to locate the next PRD. It does not use the address in the PRD Table Address Register to get the next PRD. Since Address_3 is the location of PRD_1, the bus master has looped the PRD table. Stopping the bus master can be accomplished by not reading the SMI Status Register End of Page status flag. This leads to a second EOP which causes a Bus Master Error and pauses the bus master. In effect, once a bus master has been enabled it never needs to be disabled, just paused. The bus master cannot be disabled unless the bus master has been paused or has reached an EOT. 3.7.1.5 AC97 Codec Interface The CS5530A provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec which supports sample rate conversion (SRC) can be used with the CS5530A. This type of codec allows for a design which meets the requirements for PC97 and PC98-compliant audio as defined by Microsoft Corporation. The AC97 codec (e.g., National's LM4548) is the master of the serial interface and generates the clocks to CS5530A, Figure 3-21 shows the codec and CS5530A signal connections. For specifications on the serial interface, refer to the appropriate codec manufacturer's data sheet. For PC speaker synthesis, the CS5530A outputs the PC speaker signal on the PC_BEEP pin which is connected to the PC_BEEP input of the AC97 codec.
External Source
BITCLK GeodeTM CS5530A I/O Companion SYNC PC_BEEP SDAT_I SDAT_O
BIT_CLK
24.576MHz Codec SYNC PC_BEEP SDATA_IN SDATA_OUT
AC97
Figure 3-21. AC97 Signal Connections
Codec Configuration/Control Registers The codec related registers consist of four 32-bit registers: * * * * Codec GPIO Status Register Codec GPIO Control Register Codec Status Register Codec Command Register
Codec GPIO Status and Control Registers (F3BAR+ Memory Offset 00h and 04h) The Codec GPIO Status and Control Registers are used for codec GPIO related tasks such as enabling a codec GPIO interrupt to cause an SMI. Codec Status Register (F3BAR+Memory Offset 08h) The Codec Status Register stores the codec status word. It updates every valid Status Word slot. Codec Control Register (F3BAR+Memory Offset 0Ch) The Codec Control Register writes the control word to the codec. By writing the appropriate control words to this port, the features of the codec can be controlled. The contents of this register are written to the codec during the Control Word slot. The bit formats for these registers are given in Table 3-66.
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Table 3-66. Codec Configuration/Control Registers
Bit Description Codec GPIO Status Register (R/W) Reset Value = 00100000h
F3BAR+Memory Offset 00h-03h 31 30
Codec GPIO Interface: 0 = Disable; 1 = Enable. Codec GPIO SMI: Allow codec GPIO interrupt to generate an SMI. 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1].
29:21 20 19:0
Reserved: Set to 0. Codec GPIO Status Valid (Read Only): Is the status read valid? 0 = Yes; 1 = No. Codec GPIO Pin Status (Read Only): This is the GPIO pin status that is received from the codec in slot 12 on SDATA_IN signal. Codec GPIO Control Register (R/W) Reset Value = 00000000h
F3BAR+Memory Offset 04h-07h 31:20 19:0 Reserved: Set to 0.
Codec GPIO Pin Data: This is the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal. Codec Status Register (R/W) Reset Value = 00000000h
F3BAR+Memory Offset 08h-0Bh 31:24 23
Codec Status Address (Read Only): Address of the register for which status is being returned. This address comes from slot 1 bits [19:12]. Codec Serial INT SMI: Allow codec serial interrupt to generate an SMI. 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1].
22 21 20 19 18 17 16 15:0
SYNC Pin: Selects SYNC pin level. 0 = Low; 1 = High. Enable SDATA_IN2: Pin AE24 function selection. 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). Audio Bus Master 5 AC97 Slot Select: Selects slot for Audio Bus Master 5 to receive data. 0 = Slot 6; 1 = Slot 11. Audio Bus Master 4 AC97 Slot Select: Selects slot for Audio Bus Master 4 to transmit data. 0 = Slot 6; 1 = Slot 11. Reserved: Set to 0. Status Tag (Read Only): Determines if the status in bits [15:0] is new or not. 0 = Not new; 1 = New. Codec Status Valid (Read Only): Is the status in bits [15:0] valid? 0 = No; 1 = Yes. Codec Status (Read Only): This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits [19:4] are used from slot 2. Codec Command Register (R/W) Reset Value = 00000000h
F3BAR+Memory Offset 0Ch-0Fh 31:24 23:22
Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. CS5530A Codec Communication: Selects which codec to communicate with. 00 = Primary codec 10 = Third codec 01 = Secondary codec 11 = Fourth codec Note: 00 and 01 are the only valid settings for these bits. Reserved: Set to 0. Codec Command Valid: Is the command in bits [15:0] valid? 0 = No; 1 = Yes. This bit is set by hardware when a command is loaded. It remains set until the command has been sent to the codec. Codec Command: This is the command being sent to the codec in bits [19:12] of slot 2 on SDATA_OUT.
21:17 16 15:0
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3.7.2 VSA Technology Support Hardware The CS5530A I/O companion incorporates the required hardware in order to support the Virtual System Architecture (VSA) technology for capture and playback of audio using an external codec. This eliminates much of the hardware traditionally associated with industry standard audio functions. XpressAUDIO software provides 16-bit compatible sound. This software is available to OEMs for incorporation into the system BIOS ROM. 3.7.2.1 VSA Technology VSA technology provides a framework to enable software implementation of traditionally hardware-only components. VSA technology software executes in System Management Mode (SMM), enabling it to execute transparently to the operating system, drivers, and applications. The VSA technology design is based upon a simple model for replacing hardware components with software. Hardware to be virtualized is merely replaced with simple access detection circuitry which asserts the SMI# (System Management Interrupt) pin when hardware accesses are detected. The current execution stream is immediately preempted, and the processor enters SMM. The SMM system software then saves the processor state, initializes the VSA technology execution environment, decodes the SMI source and dispatches handler routines which have registered requests to service the decoded SMI source. Once all handler routines have completed, the processor state is restored and normal execution resumes. In this manner, hardware accesses are transparently replaced with the execution of SMM handler software. Historically, SMM software was used primarily for the single purpose of facilitating active power management for notebook designs. That software's only function was to manage the power up and down of devices to save power. With high performance processors now available, it is feasible to implement, primarily in SMM software, PC capabilities traditionally provided by hardware. In contrast to power management code, this virtualization software generally has strict performance requirements to prevent application performance from being significantly impacted. 3.7.2.2 Audio SMI Related Registers The SMI related registers consist of: * Second Level Audio SMI Status Registers * I/O Trap SMI and Fast Write Status Register * I/O Trap SMI Enable Register The Top SMI Status Mirror and Status Registers are the top level of hierarchy for the SMI handler in determining the source of an SMI. These two registers are at F1BAR+Memory Offset 00h (Status Mirror) and F1BAR+Memory Offset 02h (Status). The registers are identical except that reading the register at F1BAR+Memory Offset 02h clears the status. Second Level Audio SMI Status Registers The second level of audio SMI status reporting is set up very much like the top level. There are two status reporting registers, one "read only" (mirror) and one "read to clear". The data returned by reading either offset is the same (i.e., SMI was caused by an audio related event). The difference between F3BAR+Memory Offset 12h and 10h (mirror) is in the ability to clear the SMI source at 10h. Figure 3-22 shows an SMI tree for checking and clearing the source of an audio SMI. Only the audio SMI bit is detailed here. For details regarding the remaining bits in the Top SMI Status Mirror and Status Registers refer to Table 4-17 "F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers" on page 183. I/O Trap SMI and Fast Write Status Register This 32-bit read-only register (F3BAR+Memory Offset 14h) not only indicates if the enabled I/O trap generated an SMI, but also contains Fast Path Write related bits. I/O Trap SMI Enable Register The I/O Trap SMI Enable Register (F3BAR+Memory Offset 18h) allows traps for specified I/O addresses and configures generation for I/O events. It also contains the enabling bit for Fast Path Write/Read features. If Status Fast Path Read is enabled, the CS5530A intercepts and responds to reads to several status registers. This speeds up operations, and prevents SMI generation for reads to these registers. Status Fast Path Read is enabled via F3BAR+Memory Offset 18h[4]. In Status Fast Path Read the CS5530A responds to reads of the following addresses: 388h-38Bh 2x0h, 2x1h, 2x2h, 2x3h, 2x8h, and 2x9h Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. If Fast Path Write is enabled, the CS5530A captures certain writes to several I/O locations. This feature prevents two SMIs from being asserted for write operations that are known to take two accesses (the first access is an index and the second is data). Fast Path Write is enabled via F3BAR+Memory Offset 18h[11]. Fast Path Write captures the data and address bit 1 (A1) of the first access, but does not generate an SMI. A1 is stored in F3BAR+Memory Offset 14h[15]. The second access causes an SMI, and the data and address are captured as in a normal trapped I/O. In Fast Path Write, the CS5530A responds to writes to the following addresses: 388h, 38Ah, and 38Bh 2x0h, 2x2h, and 2x8h
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Table 3-67 on page 125 and Table 3-68 on page 127 show the bit formats of the second and third level SMI status reporting registers, respectively. Table 3-69 on page 128 shows the sound card I/O trap and Fast Path Read/Write programming bits.
SMI# Asserted
SMM software reads SMI Header If Bit X = 1 (External SMI) If Bit X = 0 (Internal SMI)
GeodeTM GX-Series Processor GeodeTM CS5530A I/O Companion
F1BAR+Memory Offset 02h Read to Clear to determine top-level source of SMI
Call internal SMI handler to take appropriate action
SMI Deasserted after all SMI Sources are Cleared (i.e., Top, Second, and Third Levels)
F3BAR+Memory Offset 10h Read to Clear to determine second-level source of SMI Bits [15:8] RSVD Bits [15:2] Other_SMI Bit 7 ABM5_SMI Bit 6 ABM4_SMI Bit 5 ABM3_SMI If bit 1 = 1, Source of SMI is Audio Event Bit 4 ABM2_SMI Bit 3 ABM1_SMI Bit 2 ABM0_SMI Bit 1 SER_INTR_SMI Bit 0 I/O_TRAP_SMI Second Level Take Appropriate Action F3BAR+Memory Offset 14h Read to Clear to determine third-level source of SMI Bits [31:14] Other_RO Bit 13 SMI_SC/FM_TRAP If bit 0 = 1, Source of SMI is I/O Trap Bit 12 SMI_DMA_TRAP Bit 11 SMI_MPU_TRAP Bit 10 SMI_SC/FM_TRAP Bit [9:0] Other_RO Third Level Take Appropriate Action
Bit 1 AUDIO_SMI Bit 0 Other_SMI Top Level
Figure 3-22. Audio SMI Tree Example
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Table 3-67. Second Level SMI Status Reporting Registers
Bit Description Second Level Audio SMI Status Register (RC) Reset Value = 0000h
F3BAR+Memory Offset 10h-11h 15:8 7 Reserved: Set to 0.
Audio Bus Master 5 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 5? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1).
6
Audio Bus Master 4 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 4? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1).
5
Audio Bus Master 3 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 3? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1).
4
Audio Bus Master 2 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 2? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1).
3
Audio Bus Master 1 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 1? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1).
2
Audio Bus Master 0 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 0? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1).
1
Codec Serial or GPIO Interrupt SMI Status (Read to Clear): SMI was caused by a serial or GPIO interrupt from codec? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1.
0
I/O Trap SMI Status (Read to Clear): SMI was caused by an I/O trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1].
Note: Reading this register clears the status bits. Note that bit 0 has another level (third) of SMI status reporting. A read-only "Mirror" version of this register exists at F3BAR+Memory Offset 12h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.
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Table 3-67. Second Level SMI Status Reporting Registers (Continued)
Bit Description Second Level Audio SMI Status Mirror Register (RO) Reset Value = 0000h
F3BAR+Memory Offset 12h-13h 15:8 7 Reserved: Set to 0.
Audio Bus Master 5 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 5? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1).
6
Audio Bus Master 4 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 4? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1).
5
Audio Bus Master 3 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 3? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1).
4
Audio Bus Master 2 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 2? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1).
3
Audio Bus Master 1 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 1? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1).
2
Audio Bus Master 0 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 0? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1).
1
Codec Serial or GPIO Interrupt SMI Status (Read Only): SMI was caused by a serial or GPIO interrupt from codec? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1.
0
I/O Trap SMI Status (Read Only): SMI was caused by an I/O trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1].
Note: Reading this register does not clear the status bits. See F3BAR+Memory Offset 10h.
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Table 3-68. Third Level SMI Status Reporting Registers
Bit Description I/O Trap SMI and Fast Write Status Register (RO/RC) Reset Value = 00000000h
F3BAR+Memory Offset 14h-17h 31:24 23:16 15 14 13
Fast Path Write Even Access Data (Read Only): These bits contain the data from the last Fast Path Write Even access. These bits change only on a fast write to an even address. Fast Path Write Odd Access Data (Read Only): These bits contain the data from the last Fast Path Write Odd access. These bits change on a fast write to an odd address, and also on any non-fast write. Fast Write A1 (Read Only): This bit contains the A1 value for the last Fast Write access. Read or Write I/O Access (Read Only): Last trapped I/O access was a read or a write? 0 = Read; 1 = Write. Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM I/O Trap? 0 = No; 1 = Yes. (Note) Fast Path Write must be enabled, F3BAR+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is disabled, the SMI is reported in bit 10 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2].
12
DMA Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the DMA I/O Trap? 0 = No; 1 = Yes. (Note) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[8:7].
11
MPU Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the MPU I/O Trap? 0 = No; 1 = Yes. (Note) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[6:5].
10
Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM I/O Trap? 0 = No; 1 = Yes. (Note) Fast Path Write must be disabled, F3BAR+Memory Offset 18h[11] = 0, for the SMI to be reported here. If Fast Path Write is enabled, the SMI is reported in bit 13 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2].
9:0
X-Bus Address (Read Only): Bits [9:0] contain the captured ten bits of X-Bus address.
Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of the DMA, MPU, or sound card status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set to a 1.
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Table 3-69. Sound Card I/O Trap and Fast Path Enable Registers
Bit Description I/O Trap SMI Enable Register (R/W) Reset Value = 0000h
F3BAR+Memory Offset 18h-19h 15:12 11 Reserved: Set to 0.
Fast Path Write Enable: Fast Path Write (an SMI is not generated on certain writes to specified addresses). 0 = Disable; 1 = Enable. In Fast Path Write, the CS5530A responds to writes to the following addresses: 388h, 38Ah and 38Bh; 2x0h, 2x2h, and 2x8h.
10:9 8
Fast Read: These two bits hold part of the response that the CS5530A returns for reads to several I/O locations. High DMA I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port C0h-DFh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12].
7
Low DMA I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 00h-0Fh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12].
6
High MPU I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 330h and 331h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11].
5
Low MPU I/O Trap: I0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 300h and 301h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11].
4
Fast Path Read Enable/SMI Disable: Read Fast Path (an SMI is not generated on reads from specified addresses). 0 = Disable; 1 = Enable. In Fast Path Read the CS5530A responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1h, 2x2h, 2x3h, 2x8h and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible.
3
FM I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 388h to 38Bh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0].
2
Sound Card I/O Trap: 0 = Disable; 1 = Enable If this bit is enabled and an access occurs in the address ranges selected by bits [1:0], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[10].
1:0
Sound Card Address Range Select: These bits select the address range for the sound card I/O trap. 00 = I/O Port 220h-22Fh 01 = I/O Port 240h-24Fh 10 = I/O Port 260h-26Fh 11 = I/O Port 280h-28Fh
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3.7.2.3 IRQ Configuration Registers The CS5530A provides the ability to set and clear IRQs internally through software control. If the IRQs are configured for software control, they will not respond to external hardware. There are three registers provided for this feature: * Internal IRQ Enable Register * Internal IRQ Mask Register * Internal IRQ Control Register Internal IRQ Enable Register This register configures the IRQs as internal (software) interrupts or external (hardware) interrupts. Any IRQ used as an internal software driven source must be configured as internal. Internal IRQ Mask Register Each bit in the Mask register individually disables the corresponding bit in the Control Register. Internal IRQ Control Register This register allows individual software assertion/deassertion of the IRQs that are enabled as internal and unmasked. The bit formats for these registers are given in Table 3-70.
Table 3-70. IRQ Configuration Registers
Bit Description Internal IRQ Enable Register (R/W) Reset Value = 0000h
F3BAR+Memory Offset 1Ah-1Bh 15 14 13 12 11 10 9 8 7 6 5 4 3 2:0
IRQ15 Internal: Configure IRQ15 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ14 Internal: Configure IRQ14 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0. IRQ12 Internal: Configure IRQ12 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ11 Internal: Configure IRQ11 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ10 Internal: Configure IRQ10 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ9 Internal: Configure IRQ9 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0. IRQ7 Internal: Configure IRQ7 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0. IRQ5 Internal: Configure IRQ5 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ4 Internal: Configure IRQ4 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ3 Internal: Configure IRQ3 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0.
Note: Must be read and written as a WORD. F3BAR+Memory Offset 1Ch-1Dh 15 14 13 12 11 10 9 8 7 6 5 4 Internal IRQ Control Register (R/W) Reset Value = 0000h
Assert Masked Internal IRQ15: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ14: 0 = Disable; 1 = Enable. Reserved: Set to 0. Assert Masked Internal IRQ12: 0 = Disable; 1 = Enable. Assert masked internal IRQ11: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ10: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ9: 0 = Disable; 1 = Enable. Reserved: Set to 0. Assert Masked Internal IRQ7: 0 = Disable; 1 = Enable. Reserved: Set to 0. Assert Masked Internal IRQ5: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ4: 0 = Disable; 1 = Enable.
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Table 3-70. IRQ Configuration Registers (Continued)
Bit 3 2:0 Description Assert Masked Internal IRQ3: 0 = Disable; 1 = Enable. Reserved: Set to 0. Internal IRQ Mask Register (Write Only) Reset Value = xxxxh
F3BAR+Memory Offset 1Eh-1Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2:0
Mask Internal IRQ15: 0 = Disable; 1 = Enable. Mask Internal IRQ14: 0 = Disable; 1 = Enable. Reserved: Set to 0. Mask Internal IRQ12: 0 = Disable; 1 = Enable. Mask Internal IRQ11: 0 = Disable; 1 = Enable. Mask Internal IRQ10: 0 = Disable; 1 = Enable. Mask Internal IRQ9: 0 = Disable; 1 = Enable. Reserved: Set to 0. Mask Internal IRQ7: 0 = Disable; 1 = Enable. Reserved: Set to 0. Mask Internal IRQ5: 0 = Disable; 1 = Enable. Mask Internal IRQ4: 0 = Disable; 1 = Enable. Mask Internal IRQ3: 0 = Disable; 1 = Enable. Reserved: Set to 0.
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3.8 DISPLAY SUBSYSTEM EXTENSIONS
Figure 3-23 shows the data path of the display subsystem extensions. 3.8.1 Video Interface Configuration Registers Registers for configuring the video interface are accessed through F4 Index 10h, the Base Address Register (F4BAR) in Function 4. F4BAR sets the base address for the Video Interface Configuration Registers as shown in Table 3-71. Note: All Video Interface Configuration Registers have a 32-bit access granularity (only). The CS5530A incorporates extensions to the GX-series processors' display subsystem. These include: * Video Interface Configuration Registers -- Line Buffers -- Video Port Protocol -- Video Format -- X and Y Scaler / Filter -- Color-Space-Converter * Video Accelerator * Gamma RAM * Display Interface -- Video DACs -- VESA DDC2B / DPMS -- Flat Panel Support
The following subsections describe the video interface and the registers used for programming purposes. However, for complete bit information refer to Section 4.3.5 "Video Controller Registers - Function 4" on page 203.
Table 3-71. Base Address Register (F4BAR) for Video Controller Support Registers
Bit Description Base Address Register -- F4BAR (R/W) Reset Value = 00000000h
F4 Index 10h-13h
This register sets the base address of the memory mapped video controller registers. Bits [11:0] are read only (0000 0000 0000), indicating a 4 KB memory address range. Refer to Table 4-23 for the video controller register bit formats and reset values. 31:12 11:0 Video Controller and Clock Control Base I/O Address Address Range (Read Only)
Input Formatter
Buffer 0
24
Buffer 1 VID_DATA[7:0]
8
Formatter / Scaler
Vertical Filter
Horizontal Filter
Color Space Converter
Buffer 2
(3x360x32 bit) 24
Video
Color Key Register
24 24
Color Compare
24
Enable Gamma Correction Register
24
PIXEL[23:0]
Bypass
24 8 each
Dither
DAC
18
FP_DATA RGB to CRT
24
Gamma RAM
Figure 3-23. 8-Bit Display Subsystem Extensions
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3.8.2 Video Accelerator The CS5530A off-loads the processor from several computing-intensive tasks related to the playback of full motion video. By incorporating this level of hardware-assist, a CS5530A/GX-series processor based system can sustain 30 frames-per-second of MPEG quality video. 3.8.2.1 Line Buffers The CS5530A accepts an 8-bit video stream from the processor and provides three full MPEG resolution line buffers (3x360x32-bit). MPEG source horizontal resolutions up to 720 pixels are supported. By having three line buffers, the display pipeline can read from two lines while the next line of data is being loaded from the processor. This minimizes memory bandwidth utilization by requiring that a source line be transferred only once per frame. Peak bandwidth is also reduced by requiring that the video source line be transferred within the horizontal line time rather than forcing the transfer to occur during the active video window. This efficient utilization of memory bandwidth allows the processor and graphics accelerator an increased opportunity to access the memory subsystem and improves overall system performance during video playback. 3.8.2.2 Video Port Protocol The video port operates at one-half the processor's core clock rate and utilizes a two-wire handshake protocol. The VID_VAL input signal indicates that valid data has been placed on the VID_DATA[7:0] bus. When the CS5530A is ready to accept data, it asserts VID_RDY to indicate that a line buffer is free to accept the next line. When both VID_VAL and VID_RDY are asserted, VID_DATA advances. The VID_RDY signal is driven by the CS5530A one clock early to the processor while the VID_VAL signal is driven by the processor coincident with valid data on VID_DATA. A sample timing diagram is shown in Figure 3-24.
VID_CLK
VID_VAL
8 CLKs
8 + 2CLKs
VID_RDY
2 CLKs
VID_DATA[7:0]
3 CLKs
8 CLKs Note: VID_CLK = CORE_CLK/2
Figure 3-24. Video Port Protocol
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3.8.2.3 Video Format The video input data can be in interleaved YUV 4:2:2 or RGB 5:6:5 format. The sequence of the individual YUV components is selectable to one of four formats via bits [3:2] in the Video Configuration Register (F4BAR+Memory Offset 00h[3:2]). The decode for these bits is shown in Table 3-72.
Table 3-72. Video Input Format Bits
Bit Description Video Configuration Register (R/W) Reset Value = 00000000h
F4BAR+Memory Offset 00h-03h 31 30 29 Reserved: Set to 0
High Speed Timing for Video Interface: High speed timings for the video interface. 0 = Disable; 1= Enable. If bit 30 is enabled, bit 25 should be set to 0. 16-bit Video Interface: Allow video interface to be 16 bits. 0 = Disable; 1= Enable. If bit 29 is enabled, 8 bits of pixel data is used for video. The 24-bit pixel data is then dithered to 16 bits. Note: F4BAR+Memory Offset 04h[25] should be set to the same value as this bit (bit 29).
28
YUV 4:2:2 or 4:2:0 Mode: 0 = 4:2:2 mode; 1= 4:2:0 mode. If 4:2:0 mode is selected, bits [3:2] should be set to 01 for 8-bit video mode and 10 for 16-bit video mode. Note: The GX-series processor does not support 4:2:0 mode.
27 26 25
Video Line Size (DWORDs): This is the MSB of the Video Line Size (DWORDs). See bits [15:8] for description. Reserved: Set to 0 Early Video Ready: Generate VID_RDY output signal one-half VID_CLK period early to improve the speed of the video port operation. 0 = Disable; 1 = Enable. If bit 30 is enabled, this bit (bit 25) should be set to 0. Initial Buffer Read Address: This is the MSB of the Initial Buffer Read Address. See bits [23:16] for description. Initial Buffer Read Address: This field is used to preload the starting read address for the line buffers at the beginning of each display line. It is used for hardware clipping of the video window at the left edge of the active display. It represents the DWORD address of the source pixel which is to be displayed first. For an unclipped window, this value should be 0. Video Line Size (DWORDs): This field represents the horizontal size of the source video data in DWORDs. Y Filter Enable: Vertical filter. 0 = Disable; 1= Enable. X Filter Enable: Horizontal filter. 0 = Disable; 1 = Enable. CSC Bypass: Allows color-space-converter to be bypassed. Primarily used for displaying an RGB graphics overlay rather than a YUV video overlay. 0 = Overlay data passes through CSC; 1 = Overlay data bypasses CSC. GV Select: Selects whether graphics or video data will be passed through the scaler hardware. 0 = Video data; 1 = Graphics data. Video Input Format: This field defines the byte ordering of the video data on the VID_DATA bus. 8-Bit Mode (Value Byte Order [0:3]) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 01 = Y1 V Y0 U or 4:2:0 10 = Y0 U Y1 V 11 = Y0 V Y1 U Note: U = Cb, V = Cr 16-Bit Mode (Value Byte Order [0:3]) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 01 = Y0 U Y1 V 10 = Y1 V Y0 U or 4:2:0 11 = Reserved
24 23:16
15:8 7 6 5 4 3:2
If bit 28 is set for 4:2:0 mode, these bits (bits [3:2]) should be set to 01 for 8-bit video mode and 10 for 16-bit video mode. 1 0 Video Register Update: Allow video position and scale registers to be updated simultaneously on next occurrence of vertical sync. 0 = Disable; 1 = Enable. Video Enable: Video acceleration hardware. 0 = Disable; 1 = Enable.
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3.8.2.4 X and Y Scaler / Filter The CS5530A supports horizontal and vertical scaling of the video stream up to eight times the source resolution. The scaler uses a Digital-Differential-Analyzer (DDA) based upon the values programmed in the Video Scale Register (F4BAR+Memory Offset 10h, see Table 3-73) The scaled video stream is then passed through horizontal and vertical filters which perform a 2-tap, 8-phase bilinear filter on the resulting stream. The filtering function removes the "blockiness" of the scaled video thereby significantly improving the quality of the displayed image. By performing the scaling and filtering function in hardware, video performance is substantially improved over pure software implementations by requiring that the decompression software only output the video stream at the native source resolution. This saves both processor overhead and memory bandwidth. 3.8.2.5 Color-Space-Converter After scaling and filtering have been applied, the YUV video data is passed through the color-space converter to obtain 24-bit RGB video data. The color-space conversion equations are based on the CCIR Recommendation 601-1 as follows: R = 1.164(Y-16) + 1.596(V-128) G = 1.164(Y-16) - 0.813(V-128) - 0.391(U-128) B = 1.164(Y-16) + 2.018(U-128) The color-space converter clamps inputs to acceptable limits if the data is not well behaved. The color-space converter is bypassed for overlaying 16 bpp RGB graphics data.
Table 3-73. Video Scale Register
Bit Description Video Scale Register (R/W) Reset Value = xxxxxxxxh
F4BAR+Memory Offset 10h-13h 31:30 29:16 Reserved: Set to 0.
Video Y Scale Factor: This field represents the video window vertical scale factor according to the following formula. VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1) Where: Ys = Video source vertical size in lines Yd = Video destination vertical size in lines
15:14 13:0
Reserved: Set to 0. Video X Scale Factor: This field represents the video window horizontal scale factor according to the following formula. VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1) Where: Xs = Video source horizontal size in pixels Xd = Video destination horizontal size in pixels
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3.8.3 Video Overlay The video data from the color-space converter is then mixed with the graphics data based upon the video window position. The video window position is programmable via the Video X and Y Position Registers (F4BAR+Memory Offset 08h and 0Ch). A color-keying mechanism is employed to compare either the source (video) or destination (graphics) color to the color key programmed via the Video Color Key Register (FBAR+Offset 14h) and to select the appropriate pixel for display within the video window. The range of the color key is programmable by setting the appropriate bits in the Video Color Mask Register (F4BAR+Memory Offset 18h). This mechanism greatly reduces the software overhead for computing visible pixels, and ensures that the video display window may be partially occluded by overlapping graphics data. Tables 3-74 and 375 show the bit formats for these registers The CS5530A accepts graphics data over the PIXEL[23:0] interface from the GX-series processor at the screen DOT clock rate. The CS5530A is capable of displaying graphics resolutions up to 1600x1200 at color depths up to 24 bits per pixel (bpp) while simultaneously overlaying a video window. However, system maximum resolution is not determined by the CS5530A since it is not the source of the graphics data and timings.
Table 3-74. Video X and Y Position Registers
Bit Description Video X Register (R/W) Reset Value = xxxxxxxxh
F4BAR+Memory Offset 08h-0Bh 31:27 26:16 15:11 10:0 Reserved: Set to 0.
Video X End Position: This field represents the horizontal end position of the video window according to the following formula. Position programmed = screen position + (H_TOTAL - H_SYNC_END) - 13. Reserved: Set to 0. Video X Start Position: This field represents the horizontal start position of the video window according to the following formula. Position programmed = screen position + (H_TOTAL - H_SYNC_END) - 13. Video Y Register (R/W) Reset Value = xxxxxxxxh
F4BAR+Memory Offset 0Ch-0Fh 31:27 26:16 15:11 10:0 Reserved: Set to 0.
Video Y End Position: This field represents the vertical end position of the video window according to the following formula. Position programmed = screen position + (V_TOTAL - V_SYNC_END) + 1. Reserved: Set to 0. Video Y Start Position: This field represents the vertical start position of the video window according to the following formula. Position programmed = screen position + (V_TOTAL - V_SYNC_END) + 1.
Table 3-75. Video Color Registers
Bit Description Video Color Key Register (R/W) Reset Value = xxxxxxxxh
F4BAR+Memory Offset 14h-17h 31:24 23:0 Reserved: Set to 0.
Video Color Key: This field represents the video color key. It is a 24-bit RGB value. The graphics or video data being compared may be masked prior to the compare by programming the Video Color Mask Register (F4BAR+Memory Offset 18h) appropriately. Video Color Mask Register (R/W) Reset Value = xxxxxxxxh
F4BAR+Memory Offset 18h-1Bh 31:24 23:0 Reserved: Set to 0.
Video Color Mask: This field represents the video color mask. It is a 24-bit RGB value. Zeroes in the mask cause the corresponding bits in the graphics or video stream being compared to be ignored.
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3.8.4 Gamma RAM Either the graphics or video stream may be routed through an on-chip gamma RAM (3x256x8-bit) which can be used for gamma-correction of either data stream, or contrast/brightness adjustments in the case of video data. A bypass path is provided for either the graphics or video stream (depending on which is sent through the gamma RAM). The two streams are merged based on the results of the color key compare. Configuration for this feature and the display interface are through the Display Configuration Register (F4BAR+Memory Offset 04h). Table 3-76 shows the bit formats for this register.
Table 3-76. Display Configuration Register
Bit Description Display Configuration Register (R/W) Reset Value = 00000000h
F4BAR+Memory Offset 04h-07h 31 30:28 27 26 25 24 23 22 21 20 19:17 16:14
DDC Input Data (Read Only): This is the DDC input data bit for reads. Reserved: Set to 0. Flat Panel On (Read Only): This bit indicates whether the attached flat panel display is powered on or off. The bit transitions at the end of the power-up or power-down sequence. 0 = Off; 1 = On. Reserved: Set to 0. 16-Bit Graphics Enable: This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset 00h[29]. This bit should be set to the same value as the 16-bit Video Interface bit. DDC Output Enable: This bit enables the DDC_SDA line to be driven for write data. 0 = DDC_SDA (pin M4) is an input; 1 = DDC_SDA (pin M4) is an output. DDC Output Data: This is the DDC data bit. DDC Clock: This is the DDC clock bit. It is used to clock the DDC_SDA bit. Palette Bypass: Selects whether graphics or video data should bypass the gamma RAM. 0 = Video data; 1 = Graphics data. Video/Graphics Color Key Select: Selects whether the video or graphics data stream will be used for color/chroma keying. 0 = Graphics data is compared to color key; 1 = Video data is compared to color key. Power Sequence Delay: This field selects the number of frame periods that transpire between successive transitions of the power sequence control lines. Valid values are 001 to 111. CRT Sync Skew: This 3-bit field represents the number of pixel clocks to skew the horizontal and vertical syncs that are sent to the CRT. This field should be programmed to 100 as the baseline. The syncs may be moved forward or backward relative to the pixel data via this register. It is used to compensate for the pipeline delay through the graphics pipeline. Flat Panel Dither Enable: This bit enables flat panel dithering. It enables 24 bpp display data to be approximated with an 18-bit flat panel display. 0 = Disable; 1 = Enable. XGA Flat Panel: This bit enables the FP_CLK_ EVEN output signal which can be used to demultiplex the FP_DATA bus into even and odd pixels. 0 = Standard flat panel; 1 = XGA flat panel. Flat Panel Vertical Synchronization Polarity: Selects the flat panel vertical sync polarity. 0 = FP vertical sync is normally low, transitioning high during sync interval. 1 = FP vertical sync is normally high, transitioning low during sync interval. Flat Panel Horizontal Synchronization Polarity: Selects the flat panel horizontal sync polarity. 0 = FP horizontal sync is normally low, transitioning high during sync interval. 1 = FP horizontal sync is normally high, transitioning low during sync interval. CRT Vertical Synchronization Polarity: Selects the CRT vertical sync polarity. 0 = CRT vertical sync is normally low, transitioning high during sync interval. 1 = CRT vertical sync is normally high, transitioning low during sync interval.
13 12 11
10
9
8
CRT Horizontal Synchronization Polarity: Selects the CRT horizontal sync polarity. 0 = CRT horizontal sync is normally low, transitioning high during sync interval. 1 = CRT horizontal sync is normally high, transitioning low during sync interval. Flat Panel Data Enable: Enables the flat panel data bus. 0 = FP_DATA [17:0] is forced low; 1 = FP_DATA [17:0] is driven based upon power sequence control. Flat Panel Power Enable: The transition of this bit initiates a flat panel power-up or power-down sequence. 0 -> 1 = Power-up flat panel; 1 -> 0 = Power-down flat panel. DAC Power-Down (active low): This bit must be set to power-up the video DACs. It can be cleared to power-down the video DACs when not in use. 0 = DACs are powered down; 1 = DACs are powered up. Reserved: Set to 0.
7
6
5 4
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Table 3-76. Display Configuration Register (Continued)
Bit 3 2 1 0 Description DAC Blank Enable: This bit enables the blank to the video DACs. 0 = DACs are constantly blanked; 1 = DACs are blanked normally. CRT Vertical Sync Enable: Enables the CRT vertical sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. CRT Horizontal Sync Enable: Enables the CRT horizontal sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. Display Enable: Enables the graphics display pipeline. It is used as a reset for the display control logic. 0 = Reset display control logic; 1 = Enable display control logic.
3.8.5 Display Interface The CS5530A interfaces directly to a variety of display devices including conventional analog CRT displays, TFT flat panels, the National's Geode CS9211 graphics companion (a flat panel display controller), or optionally to digital NTSC/PAL encoder devices. 3.8.5.1 Video DACs The CS5530A incorporates three 8-bit video Digital-to-Analog Converters (DACs) for interfacing directly to CRT displays. The video DACs meet the VESA specification and are capable of operation up to 157.5 MHz for supporting up to 1280x1024 display at a 85 Hz refresh rate and are VESA compliant. 3.8.5.2 VESA DDC2B / DPMS The CS5530A supports the VESA DDC2B and DPMS standards for enhanced monitor communications and power management support. 3.8.5.3 Flat Panel Support The CS5530A also interfaces directly to industry standard 18-bit Active Matrix Thin-Film-Transistor (TFT) flat panels. The CS5530A includes 24-bit to 18-bit dithering logic to increase the apparent number of colors displayed on 18-bit flat panels. In addition, the CS5530A incorporates power sequencing logic to simplify the design of a portable system.
The flat panel port of the CS5530A may optionally drive the CS9211 graphics companion device for color dual-scan display (DSTN) support. If flat panel support is not required, the flat panel output port may be used to supply digital video data to one of several types of NTSC/PAL encoder devices on the market. Flat Panel Power-Up/Down Sequence When the Flat Panel Power Enable bit (F4BAR+Memory Offset 04h[6]) transitions from a 0 to 1, the FP_ENA_VDD signal is enabled. This is followed by the data bus (including syncs and ENA_DISP). Finally, FP_ENA_BKL is enabled. The time between each of these successive stages is set by the value of the Power Sequence Delay bits (F4BAR+Memory Offset 04h[19:17]). The value in these bits refer to the number of graphics frames that will elapse between each successive enabling of the TFT signals. For example, if the Power Sequence Delay is set to 3h (011b), then three frame times will elapse between the time when FP_ENA_VDD is transitioned and the data bus is transitioned. Likewise, three frame times will elapse between the data bus getting enabled and the FP_ENA_BKL is transitioned. If the panel is being refreshed at 100 Hz, each frame lasts 1 ms. So, if the Power Sequence Delay is set to 3, 3 ms will elapse between transitions. When powering off the panel, the signals are transitioned in the opposite order (FP_ENA_BKL, data bus, FP_ENA_VDD) using the same Power Sequence Delay in the power-down sequence.
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Functional Description (Continued)
3.9 UNIVERSAL SERIAL BUS SUPPORT Table 3-77. USB PCI Configuration Registers
USB Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 3.9.1 USB PCI Controller The PCI controller interfaces the host controller to the PCI bus. As a master, the PCI controller is responsible for running cycles on the PCI bus on behalf of the host controller. As a target, the PCI controller monitors the cycles on the PCI bus and determines when to respond to these cycles. The USB core is a PCI target when it decodes cycles to its internal PCI configuration registers or to its internal PCI memory mapped I/O registers. The USB core is implemented as a unique PCI device in the CS5530A. It has its own PCI Header and Configuration space. It is a single-function device, containing only Function #0. Depending on the state of the HOLD_REQ# strap pin at reset, its PCI Device Number for Configuration accesses varies: If HOLD_REQ# is low, it uses pin AD29 as its IDSEL input, appearing as Device #13h in a Geode system. If HOLD_REQ# is high, it uses pin AD27 as its IDSEL input, appearing as Device #11h in a Geode system. The USB core is also affected by some bits in registers belonging to the other (Chipset) device of the CS5530A. In particular, the USB device can be disabled through the Chipset device, F0 Index 43h[0], and its IDSEL can be remapped by changing F0 Index 44h[6] (though this also affects the Chipset device's IDSEL and is not recommended). All registers can be accessed via 8-, 16-, or 32-bit cycles (i.e., each byte is individually selected by the byte enables). Registers marked as Reserved, and reserved bits within a register are not implemented and should not be modified. These registers are summarized in Table 3-77. For complete bit information, see Table 4-25 "USB Index xxh: USB PCI Configuration Registers" on page 210. 10h-13h Type RO RO R/W R/W RO RO R/W R/W RO RO R/W Name Vendor Identification Device Identification Command Register Status Register Device Revision ID Class Code Cache Line Size Latency Timer Header Type BIST Register Base Address Register (USB BAR): Sets the base address of the memory mapped USB controller registers. Reserved Interrupt Line Register Interrupt Pin Register Min. Grant Register Max. Latency Register ASIC Test Mode Enable Register ASIC Operational Mode Enable Reserved Reserved The CS5530A integrates a Universal Serial Bus (USB) controller which supports two ports. The USB controller is OpenHCI compliant, a standard developed by Compaq, Microsoft, and National Semiconductor. The USB core consists of three main interface blocks: the USB PCI interface controller, the USB host controller, and the USB interface controller. Legacy keyboard and mouse controllers are also supported for DOS compatibility with those USB devices. This document must be used along with the following public domain reference documents for a complete functional description of the USB controller: * USB Specification Revision 1.0 * OpenHCI Specification, Revision 1.0 * PCI Specification, Version 2.1
14h-3Bh 3Ch 3Dh 3Eh 3Fh 40h-43h 44h-45h 46h-47h 48h-FFh
-R/W RO RO RO R/W R/W ---
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3.9.2 USB Host Controller In the USB core is the operational control block. It is responsible for the host controller's operational states (Suspend, Disable, Enable), special USB signals (Reset, Resume), status, interrupt control, and host controller configuration. The host controller interface registers are memory mapped registers, mapped by USB F0 Index 10h (Base Address Register). These memory mapped registers are summarized in Table 3-78. For bit definitions, refer to Table 4-26 "USB BAR+Memory Offset xxh: USB Controller Registers" on page 213. 3.9.3 USB Power Management At this time, USB supports minimal system level power management features. The only power management feature implemented is the disabling of the USB clock generator in USB Suspend state. Additional power management features require slight modifications. The design supports PCICLK frequencies from 0 to 33 MHz. Synchronization between the PCI and USB clock domains is frequency independent. Remote wakeup of USB is asynchronously implemented from the USB Ports to PCI INTA#. The design needs USBCLK to be operational at all times. If it is necessary to stop the 48 MHz clock, the system design requires that the signal used to enable/disable the USB clock generators is also used to wake the 48 MHz clock source. Currently, the RemoteWakeupConnected and RemoteWakeupEnable bits in the HcControl register are not implemented.
Table 3-78. USB Controller Registers
USB BAR+ Memory Offset 00h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-3Bh 3Ch-3Fh 40h-43h 44h-47h 48h-4Bh 4Ch-4Fh 50h-53h 54h-57h 58h-5Bh 5Ch-5Fh 60h-9Fh 100h-103h 104h-107h 108h-10Dh 10Ch-10Fh
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W R/W --R/W R/W R/W R/W
Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] Reserved Reserved HceControl HceInput HceOutput HceStatus
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Register Descriptions
The ISA Legacy I/O Register Space contains all the legacy compatibility I/O ports that are internal, trapped, shadowed, or snooped. The V-ACPI I/O Register Space contains two types of registers: Fixed Feature and General Purpose. These registers are emulated by the SMI handling code rather than existing in physical hardware. To the ACPI-compliant operating system, the SMI-base virtualization is transparent. An ACPI compliant system is one whose underlying BIOS, device drivers, chipset and peripherals conform to revision 1.0 or newer of the Advanced Control and Power Interface specification. The CS5530A V-ACPI (Virtual ACPI) solution provides the following support: * CPU States -- C1, C2 * Sleep States -- S1, S2, S4, S4BIOS, S5 * Embedded Controller (Optional) -- SCI and SWI event inputs * General Purpose Events -- Fully programmable GPE0 Event Block registers The remaining subsections of this chapter are as follows: * A brief discussion on how to access the registers located in the PCI Configuration Space * Register summary * Detailed bit formats of all registers
The Geode CS5530A is a multi-function device. Its register space can be broadly divided into four categories in which specific types of registers are located: 1) 2) 3) 4) Chipset Register Space (F0-F4) USB Controller Register Space (PCIUSB) ISA Legacy I/O Register Space (I/O Port) V-ACPI I/O Register Space (I/O Port)
The Chipset and the USB Controller Register Spaces are accessed through the PCI interface using the PCI Type One Configuration Mechanism. The Chipset Register Space of the CS5530A is comprised of five separate functions (F0-F4) each with its own register space consisting of PCI header registers and memory or I/O mapped registers. F0: Bridge Configuration Registers F1: SMI Status and ACPI Timer Registers F2: IDE Controller Registers F3: XpressAUDIO Subsystem Registers F4: Video Controller Registers The PCI header is a 256-byte region used for configuring a PCI device or function. The first 64 bytes are the same for all PCI devices and are predefined by the PCI specification. These registers are used to configure the PCI for the device. The rest of the 256-byte region is used to configure the device or function itself. The USB Controller Register Space consists of the standard PCI header registers. The USB controller supports two ports and is OpenHCI-compliant.
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4.1 PCI CONFIGURATION SPACE AND ACCESS METHODS
read or write to the Configuration Data Register (CDR) causes a PCI configuration cycle to the CS5530A. BYTE, WORD, or DWORD accesses are allowed to the CDR at 0CFCh, 0CFDh, 0CFEh, or 0CFFh. The CS5530A has six configuration register sets, one for each function (F0-F4) and USB (PCIUSB). Base Address Registers (BARs) in the PCI header registers are pointers for additional I/O or memory mapped configuration registers. Table 4-1 shows the PCI Configuration Address Register (0CF8h) and how to access the PCI header registers. Configuration cycles are generated in the processor. All configuration registers in the CS5530A are accessed through the PCI interface using the PCI Type One Configuration Mechanism. This mechanism uses two DWORD I/O locations at 0CF8h and 0CFCh. The first location (0CF8h) references the Configuration Address Register. The second location (0CFCh) references the Configuration Data Register. To access PCI configuration space, write the Configuration Address (0CF8h) Register with data that specifies the CS5530A as the device on PCI being accessed, along with the configuration register offset. On the following cycle, a
Table 4-1. PCI Configuration Address Register (0CF8h)
31 Configuration Space Mapping 1 (Enable) 30 RSVD 000 0000 24 23 16 15 11 10 Function xxx 8 7 Index xxxx xx 2 1 DWORD 00 00 (Always) 0 Bus Number 0000 0000 Device Number xxxx x (Note)
Function 0 (F0): Bridge Configuration Register Space 80h 0000 0000 1001 0 or 1000 0 000 Index
Function 1 (F1): SMI Status and ACPI Timer Register Space 80h 0000 0000 1001 0 or 1000 0 001 Index
Function 2 (F2): IDE Controller Register Space 80h 0000 0000 1001 0 or 1000 0 010 Index
Function 3 (F3): XpressAUDIO Subsystem Register Space 80h 0000 0000 1001 0 or 1000 0 011 Index
Function 4 (F4): Video Controller Register Space 80h 0000 0000 1001 0 or 1000 0 100 Index
PCIUSB: USB Controller Register Space 80h 0000 0000 1001 1 or 1000 1 000 Index
Note: The device number depends upon the strapping of pin H26 (HOLD_REQ#) during POR. Strap pin H26 low: IDSEL = AD28 for Chipset Register Space and AD29 for USB Register Space Strap pin H26 high: IDSEL = AD26 for Chipset Register Space and AD27 for USB Register Space The strapping of pin H26 can be read back in F0 Index 44h[6].
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4.2 REGISTER SUMMARY
values and page references where the bit formats are found. The tables in this subsection summarize all the registers of the CS5530A. Included in the tables are the register's reset
Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary
F0 Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-1Fh 20h-3Fh 40h 41h 42h 43h 44h 45h-4Fh 50h 51h 52h 53h 54h-59h 5Ah 5Bh 5Ch 5Dh 5Eh-6Fh 70h-71h 72h 73h-7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh www.national.com Width (Bits) 16 16 16 16 8 24 8 8 8 8 --8 8 8 8 8 -8 8 8 8 -8 8 8 8 -16 8 -8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -Type RO RO R/W R/W RO RO R/W R/W RO RO --R/W R/W R/W R/W R/W -R/W R/W R/W R/W -R/W R/W R/W R/W -R/W R/W -R/W R/W R/W R/W RO RO RO RO R/W R/W R/W R/W R/W R/W R/W -Name Vendor Identification Register Device Identification Register PCI Command Register PCI Status Register Device Revision ID Register PCI Class Code Register PCI Cache Line Size Register PCI Latency Timer Register PCI Header Type Register PCI BIST Register Reserved Reserved PCI Function Control Register 1 PCI Function Control Register 2 PCI Function Control Register 3 USB Shadow Register Reset Control Register Reserved PIT Control/ISA CLK Divider ISA I/O Recovery Control Register ROM/AT Logic Control Register Alternate CPU Support Register Reserved Decode Control Register 1 Decode Control Register 2 PCI Interrupt Steering Register 1 PCI Interrupt Steering Register 2 Reserved General Purpose Chip Select Base Address Register General Purpose Chip Select Control Register Reserved Power Management Enable Register 1 Power Management Enable Register 2 Power Management Enable Register 3 Power Management Enable Register 4 Second Level Power Management Status Mirror Register 1 Second Level Power Management Status Mirror Register 2 Second Level Power Management Status Mirror Register 3 Second Level Power Management Status Mirror Register 4 General Purpose Timer 1 Count Register General Purpose Timer 1 Control Register General Purpose Timer 2 Count Register General Purpose Timer 2 Control Register IRQ Speedup Timer Count Register Video Speedup Timer Count Register VGA Timer Count Register Reserved 142 Reset Value 1078h 0100h 000Fh 0280h xxh 060100h 00h 00h 80h 00h xxh 00h 89h 10h ACh 03h 01h 00h 7Bh 40h F8h 00h xxh 03h 20h 00h 00h xxh 0000h 00h xxh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h xxh Reference (Table 4-15) Page 153 Page 153 Page 153 Page 154 Page 154 Page 154 Page 154 Page 154 Page 154 Page 154 Page 154 Page 154 Page 155 Page 155 Page 155 Page 156 Page 156 Page 156 Page 157 Page 157 Page 157 Page 157 Page 158 Page 158 Page 158 Page 159 Page 159 Page 159 Page 159 Page 159 Page 159 Page 160 Page 161 Page 162 Page 163 Page 164 Page 165 Page 166 Page 167 Page 167 Page 168 Page 168 Page 169 Page 169 Page 169 Page 169 Page 169 Revision 1.1
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Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary (Continued)
F0 Index 90h 91h 92h 93h 94h 95h 96h 97h 98h-99h 9Ah-9Bh 9Ch-9Dh 9Eh-9Fh A0h-A1h A2h-A3h A4h-A5h A6h-A7h A8h-A9h AAh-ABh ACh-ADh AEh AFh B0h-B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh-BFh C0h-C3h C4h-C7h C8h-CBh CCh CDh CEh CFh D0h D1h-EBh ECh EDh-F3h F4h F5h F6h F7h F8h-FFh Width (Bits) 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 -16 8 8 -8 8 8 8 8 8 8 8 8 -32 32 32 8 8 8 -8 -8 -8 8 8 8 -Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -R/W WO WO -RO RO RO RO RO RO RO RO R/W -R/W R/W R/W R/W R/W R/W -WO -R/W -RC RC RC RO/RC -Name GPIO Pin Direction Register 1 GPIO Pin Data Register 1 GPIO Control Register 1 Miscellaneous Device Control Register Suspend Modulation OFF Count Register Suspend Modulation ON Count Register Suspend Configuration Register GPIO Control Register 2 Primary Hard Disk Idle Timer Count Register Floppy Disk Idle Timer Count Register Parallel / Serial Idle Timer Count Register Keyboard / Mouse Idle Timer Count Register User Defined Device 1 Idle Timer Count Register User Defined Device 2 Idle Timer Count Register User Defined Device 3 Idle Timer Count Register Video Idle Timer Count Register Video Overflow Count Register Reserved Secondary Hard Disk Idle Timer Count Register CPU Suspend Command Register Suspend Notebook Command Register Reserved Floppy Port 3F2h Shadow Register Floppy Port 3F7h Shadow Register Floppy Port 1F2h Shadow Register Floppy Port 1F7h Shadow Register DMA Shadow Register PIC Shadow Register PIT Shadow Register RTC Index Shadow Register Clock Stop Control Register Reserved User Defined Device 1 Base Address Register User Defined Device 2 Base Address Register User Defined Device 3 Base Address Register User Defined Device 1 Control Register User Defined Device 2 Control Register User Defined Device 3 Control Register Reserved Software SMI Register Reserved Timer Test Register Reserved Second Level Power Management Status Register 1 Second Level Power Management Status Register 2 Second Level Power Management Status Register 3 Second Level Power Management Status Register 4 Reserved Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h xxh 0000h 00h 00h xxh xxh xxh xxh xxh xxh xxh xxh xxh 00h xxh 00000000h 00000000h 00000000h 00h 00h 00h xxh 00h xxh 00h xxh 00h 00h 00h 00h xxh Reference (Table 4-15) Page 170 Page 170 Page 170 Page 171 Page 171 Page 171 Page 171 Page 172 Page 172 Page 172 Page 172 Page 173 Page 173 Page 173 Page 173 Page 173 Page 173 Page 173 Page 174 Page 174 Page 174 Page 174 Page 174 Page 174 Page 174 Page 174 Page 175 Page 175 Page 175 Page 175 Page 176 Page 176 Page 176 Page 176 Page 176 Page 176 Page 177 Page 177 Page 177 Page 177 Page 177 Page 177 Page 177 Page 178 Page 179 Page 180 Page 181 Page 181
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Table 4-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary
F1 Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-13h Width (Bits) 16 16 16 16 8 24 8 8 8 8 32 Type RO RO R/W RO RO RO RO RO RO RO R/W Name Vendor Identification Register Device Identification Register PCI Command Register PCI Status Register Device Revision ID Register PCI Class Code Register PCI Cache Line Size Register PCI Latency Timer Register PCI Header Type Register PCI BIST Register Base Address Register (F1BAR): Sets base address for memory mapped SMI status and ACPI timer support registers (summarized in Table 4-4). Reserved Reserved Reset Value 1078h 0101h 0000h 0280h 00h 068000h 00h 00h 00h 00h 00000000h Reference (Table 4-16) Page 182 Page 182 Page 182 Page 182 Page 182 Page 182 Page 182 Page 182 Page 182 Page 182 Page 182
14h-3Fh 40h-FFh
--
--
00h xxh
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Table 4-4. F1BAR: SMI Status and ACPI Timer Registers Summary
F1BAR+ Memory Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h-09h 0Ah-1Bh 1Ch-1Fh Width (Bits) 16 16 16 16 16 -32 Reset Value 0000h 0000h 0000h 0000h 0000h xxh 00FFFFFCh Reference (Table 4-17) Page 183 Page 184 Page 185 Page 186 Page 186 Page 186 Page 186
Type RO RC RO RC Read to Enable -RO
Name Top SMI Status Mirror Register Top SMI Status Register Second Level General Traps & Timers Status Mirror Second Level General Traps & Timers Status Register SMI Speedup Disable Register Reserved ACPI Timer Count Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch.
20h-4Fh 50h-FFh
--
--
Reserved
xxh
Page 187
Note: The registers located at F1BAR+Memory Offset 50h-FFh can also be accessed at F0 Index 50h-FFh. The preferred method is to program these registers through the F0 Register Space. Refer to Table 4-2 "Function 0: PCI Header and Bridge Configuration Registers Summary" on page 142 for summary information.
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Table 4-5. Function 2: PCI Header Registers for IDE Controller Summary
F2 Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-1Fh 20h-23h Width (Bits) 16 16 16 16 8 24 8 8 8 8 -32 Type RO RO R/W RO RO RO RO RO RO RO -R/W Name Vendor Identification Register Device Identification Register PCI Command Register PCI Status Register Device Revision ID Register PCI Class Code Register PCI Cache Line Size Register PCI Latency Timer Register PCI Header Type Register PCI BIST Register Reserved Base Address Register (F2BAR): Sets base address for I/O mapped IDE controller configuration registers (summarized in Table 4-6). Reserved Reserved Reset Value 1078h 0102h 0000h 0280h 00h 010180h 00h 00h 00h 00h 00h 00000001h Reference (Table 4-18) Page 188 Page 188 Page 188 Page 188 Page 188 Page 188 Page 188 Page 188 Page 188 Page 188 Page 188 Page 188
24h-3Fh 40h-FFh
---
---
00h xxh
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Table 4-6. F2BAR: IDE Controller Configuration Registers Summary
F2BAR+ I/O Offset 00h 01h 02h 03h 04h-07h 08h 09h 0Ah 0Bh 0Ch-0Fh 10h-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-3Bh 3Ch-3Fh 40h-FFh Width (Bits) 8 -8 -32 8 -8 -32 -32 32 32 32 32 32 32 32 -Type R/W -R/W -R/W R/W -R/W -R/W -R/W R/W R/W R/W R/W R/W R/W R/W -Name IDE Bus Master 0 Command Register: Primary Reserved IDE Bus Master 0 Status Register: Primary Reserved IDE Bus Master 0 PRD Table Address: Primary IDE Bus Master 1 Command Register: Secondary Reserved IDE Bus Master 1 Status Register: Secondary Reserved IDE Bus Master 1 PRD Table Address: Secondary Reserved Channel 0 Drive 0: PIO Register Channel 0 Drive 0: DMA Control Register Channel 0 Drive 1: PIO Register Channel 0 Drive 1: DMA Control Register Channel 1 Drive 0: PIO Register Channel 1 Drive 0: DMA Control Register Channel 1 Drive 1: PIO Register Channel 1 Drive 1: DMA Control Register Reserved Reset Value 00h xxh 00h xxh 00000000h 00h xxh 00h xxh 00000000h xxh 0000E132h 00077771h 0000E132h 00077771h 0000E132h 00077771h 0000E132h 00077771h xxh Reference (Table 4-19) Page 189 Page 189 Page 189 Page 189 Page 189 Page 189 Page 189 Page 189 Page 190 Page 190 Page 190 Page 190 Page 191 Page 191 Page 191 Page 191 Page 191 Page 191 Page 191 Page 191
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Table 4-7. Function 3: PCI Header Registers for XpressAUDIO Subsystem Summary
F3 Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-13h Width (Bits) 16 16 16 16 8 24 8 8 8 8 32 Type RO RO R/W RO RO RO RO RO RO RO R/W Name Vendor Identification Register Device Identification Register PCI Command Register PCI Status Register Device Revision ID Register PCI Class Code Register PCI Cache Line Size Register PCI Latency Timer Register PCI Header Type Register PCI BIST Register Base Address Register (F3BAR): Sets base address for memory mapped XpressAUDIO subsystem configuration registers (summarized in Table 4-8). Reserved Reserved Reset Value 1078h 0103h 0000h 0280h 00h 040100h 00h 00h 00h 00h 00000000h Reference (Table 4-20) Page 192 Page 192 Page 192 Page 192 Page 192 Page 192 Page 192 Page 192 Page 192 Page 192 Page 192
14h-3Fh 40h-FFh
---
---
00h xxh
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Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary
F3BAR+ Memory Offset 00h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-11h 12h-13h 14h-17h 18h-19h 1Ah-1Bh 1Ch-1Dh 1Eh-1Fh 20h 21h 22h-23h 24h-27h 28h 29h 2Ah-2Bh 2Ch-2Fh 30h 31h 32h-33h 34h-37h 38h 39h 3Ah-3Bh 3Ch-3Fh 40h www.national.com Width (Bits) 32 32 32 32 16 16 32 16 16 16 16 8 8 -32 8 8 -32 8 8 -32 8 8 -32 8 Reference (Table 4-21) Page 193 Page 193 Page 193 Page 193 Page 194 Page 195 Page 196 Page 197 Page 198 Page 198 Page 198 Page 199 Page 199 Page 199 Page 199 Page 199 Page 200 Page 200 Page 200 Page 200 Page 200 Page 200 Page 200 Page 201 Page 201 Page 201 Page 201 Page 201 Revision 1.1
Type R/W R/W R/W R/W RO RC RO/RC R/W R/W R/W WO R/W RC -R/W R/W RC -R/W R/W RC -R/W R/W RC -R/W R/W
Name Codec GPIO Status Register Codec GPIO Control Register Codec Status Register Codec Command Register Second Level Audio SMI Source Mirror Register Second Level Audio SMI Source Register I/O Trap SMI and Fast Write Status Register I/O Trap SMI Enable Register Internal IRQ Enable Register Internal IRQ Control Register Internal IRQ Mask Register Audio Bus Master 0 Command Register Audio Bus Master 0 SMI Status Register Reserved Audio Bus Master 0 PRD Table Address Audio Bus Master 1 Command Register Audio Bus Master 1 SMI Status Register Reserved Audio Bus Master 1 PRD Table Address Audio Bus Master 2 Command Register Audio Bus Master 2 SMI Status Register Reserved Audio Bus Master 2 PRD Table Address Audio Bus Master 3 Command Register Audio Bus Master 3 SMI Status Register Reserved Audio Bus Master 3 PRD Table Address Audio Bus Master 4 Command Register 146
Reset Value 00100000h 00000000h 00000000h 00000000h 0000h 0000h 00000000h 0000h 0000h 0000h xxxxh 00h 00h xxh 00000000h 00h 00h xxh 00000000h 00h 00h xxh 00000000h 00h 00h xxh 00000000h 00h
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Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary (Continued)
F3BAR+ Memory Offset 41h 42h-43h 44h-47h 48h 49h 4Ah-4Bh 4Ch-4Fh 50h-FFh Width (Bits) 8 -32 8 8 -32 -Reference (Table 4-21) Page 202 Page 202 Page 202 Page 202 Page 202 Page 202 Page 202 Page 202
Type RC -R/W R/W RC -R/W --
Name Audio Bus Master 4 SMI Status Register Reserved Audio Bus Master 4 PRD Table Address Audio Bus Master 5 Command Register Audio Bus Master 5 SMI Status Register Reserved Audio Bus Master 5 PRD Table Address Reserved
Reset Value 00h xxh 00000000h 00h 00h xxh 00000000h xxh
Table 4-9. Function 4: PCI Header Registers for Video Controller Summary
F4 Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-13h Width (Bits) 16 16 16 16 8 24 8 8 8 8 32 Type RO RO R/W RO RO RO RO RO RO RO R/W Name Vendor Identification Device Identification PCI Command PCI Status Device Revision ID PCI Class Code PCI Cache Line Size PCI Latency Timer PCI Header Type PCI BIST Register Base Address Register (F4BAR): Sets base address for memory mapped video controller configuration registers (summarized in Table 4-10). Reserved Reserved Reset Value 1078h 0104h 0000h 0280h 00h 030000h 00h 00h 00h 00h 00000000h Reference (Table 4-22) Page 203 Page 203 Page 203 Page 203 Page 203 Page 203 Page 203 Page 203 Page 203 Page 203 Page 203
14h-3Fh 40h-FFh
---
---
00h xxh
Page 203 Page 203
x
Table 4-10. F4BAR: Video Controller Configuration Registers Summary
F4BAR+ Memory Offset 00h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-FFh Width (Bits) 32 32 32 32 32 32 32 32 32 32 32 -Reset Value 00000000h x0000000h xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh 00000000h 00000100h xxh Reference (Table 4-23) Page 204 Page 205 Page 206 Page 206 Page 206 Page 206 Page 206 Page 206 Page 206 Page 207 Page 208 Page 208
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W --
Register Name Video Configuration Register Display Configuration Register Video X Register Video Y Register Video Scale Register Video Color Key Register Video Color Mask Register Palette Address Register Palette Data Register Dot Clock Configuration Register CRC Signature and TFT/TV Configuration Register Reserved
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Table 4-11. USB PCI Configuration Registers Summary
USB Index 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-13h Width (Bits) 16 16 16 16 8 24 8 8 8 8 32 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W Name Vendor Identification Device Identification Command Register Status Register Device Revision ID Class Code Cache Line Size Latency Timer Header Type BIST Register Base Address Register (USB BAR): Sets the base address of the memory mapped USB controller registers. Refer to Table 4-26 for the USB controller register bit formats and reset values. Reserved Interrupt Line Register Interrupt Pin Register Min. Grant Register Max. Latency Register ASIC Test Mode Enable Register ASIC Operational Mode Enable Reserved Reserved Reset Value 0E11h A0F8h 0000h 0280h 06h 0C0310h 00h 00h 00h 00h 00000000h Reference (Table 4-25) Page 210 Page 210 Page 210 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211
14h-3Bh 3Ch 3Dh 3Eh 3Fh 40h-43h 44h-45h 46h-47h 48h-FFh
-8 8 8 8 32 16 ---
-R/W RO RO RO R/W R/W ---
xxh 00h 01h 00h 50h 000F0000h 0000h 00h xxh
Page 211 Page 211 Page 211 Page 212 Page 212 Page 212 Page 212 Page 212 Page 212
Table 4-12. USB BAR: USB Controller Registers Summary
USB BAR+ Memory Offset 00h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-3Bh 3Ch-3Fh 40h-43h 44h-47h 48h-4Bh 4Ch-4Fh Width (Bits) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Reference (Table 4-26) Page 213 Page 213 Page 213 Page 213 Page 214 Page 214 Page 214 Page 214 Page 214 Page 214 Page 214 Page 214 Page 214 Page 215 Page 215 Page 215 Page 215 Page 215 Page 215 Page 216
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W
Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB
Reset Value 00000110h 00000000h 00000000h 00000000h 00000000h C000006Fh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00002EDFh 00002Exxh 00000000h 00000000h 00000628h 01000002h 00000000h
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Register Descriptions (Continued)
Table 4-12. USB BAR: USB Controller Registers Summary (Continued)
USB BAR+ Memory Offset 50h-53h 54h-57h 58h-5Bh 5Ch-5Fh 60h-9Fh 100h-103h 104h-107h 108h-10Dh 10Ch-10Fh Width (Bits) 32 32 32 32 -32 32 32 32 Reference (Table 4-26) Page 216 Page 217 Page 218 Page 218 Page 218 Page 219 Page 219 Page 219 Page 219
Type R/W R/W R/W --R/W R/W R/W R/W
Name HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] Reserved Reserved HceControl HceInput HceOutput HceStatus
Reset Value 00000000h 00000628h 01000002h 00000000h xxh 00000000h 000000xxh 000000xxh 00000000h
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Table 4-13. ISA Legacy I/O Registers Summary
I/O Port Type Name Reference
DMA Channel Control Registers (Table 4-27) 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 0C0h 0C2h 0C4h 0C6h 0C8h 0CAh 0CCh 0CEh 0D0h 0D2h 0D4h 0D6h 0D8h 0DAh 0DCh 0DEh R/W R/W R/W R/W R/W R/W R/W R/W Read Write WO R/W WO WO WO WO WO R/W R/W R/W R/W R/W R/W R/W R/W Read Write WO R/W WO WO WO WO WO DMA Channel 0 Address Register DMA Channel 0 Transfer Count Register DMA Channel 1 Address Register DMA Channel 1 Transfer Count Register DMA Channel 2 Address Register DMA Channel 2 Transfer Count Register DMA Channel 3 Address Register DMA Channel 3 Transfer Count Register DMA Status Register, Channels 3:0 DMA Command Register, Channels 3:0 Software DMA Request Register, Channels 3:0 DMA Channel Mask Register, Channels 3:0 DMA Channel Mode Register, Channels 3:0 DMA Clear Byte Pointer Command, Channels 3:0 DMA Master Clear Command, Channels 3:0 DMA Clear Mask Register Command, Channels 3:0 DMA Write Mask Register Command, Channels 3:0 DMA Channel 4 Address Register (Not used) DMA Channel 4 Transfer Count Register (Not Used) DMA Channel 5 Address Register DMA Channel 5 Transfer Count Register DMA Channel 6 Address Register DMA Channel 6 Transfer Count Register DMA Channel 7 Address Register DMA Channel 7 Transfer Count Register DMA Status Register, Channels 7:4 DMA Command Register, Channels 7:4 Software DMA Request Register, Channels 7:4 DMA Channel Mask Register, Channels 7:0 DMA Channel Mode Register, Channels 7:4 DMA Clear Byte Pointer Command, Channels 7:4 DMA Master Clear Command, Channels 7:4 DMA Clear Mask Register Command, Channels 7:4 DMA Write Mask Register Command, Channels 7:4 Page 220 Page 220 Page 220 Page 220 Page 220 Page 220 Page 220 Page 220 Page 220 Page 220 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 221 Page 222 Page 222 Page 222 Page 222 Page 222 Page 222 Page 222 Page 222 Page 222 Page 222
DMA Page Registers (Table 4-28) 081h 082h 083h 087h 089h 08Ah 08Bh 08Fh 481h 482h 483h 487h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA Channel 2 Low Page Register DMA Channel 3 Low Page Register DMA Channel 1 Low Page Register DMA Channel 0 Low Page Register DMA Channel 6 Low Page Register DMA Channel 7 Low Page Register DMA Channel 5 Low Page Register ISA Refresh Low Page Register DMA Channel 2 High Page Register DMA Channel 3 High Page Register DMA Channel 1 High Page Register DMA Channel 0 High Page Register Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223
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Table 4-13. ISA Legacy I/O Registers Summary
I/O Port 489h 48Ah 48Bh Type R/W R/W R/W Name DMA Channel 6 High Page Register DMA Channel 7 High Page Register DMA Channel 5 High Page Register Reference Page 223 Page 223 Page 223
Programmable Interval Timer Registers (Table 4-29) 040h 041h 042h 043h 043h Write Read Write Read Write Read Write R/W PIT Timer 0 Counter PIT Timer 0 Status PIT Timer 1 Counter (Refresh) PIT Timer 1 Status (Refresh) PIT Timer 2 Counter (Speaker) PIT Timer 2 Status (Speaker) PIT Mode Control Word Register PIT Read-Back Command Read Status Command Counter Latch Command Programmable Interrupt Controller Registers (Table 4-30) 020h / 0A0h 021h / 0A1h 021h / 0A1h 021h / 0A1h 021h / 0A1h 020h / 0A0h 020h / 0A0h 020h / 0A0h WO WO WO WO R/W WO WO RO Master / Slave PCI IWC1 Master / Slave PIC ICW2 Master / Slave PIC ICW3 Master / Slave PIC ICW4 Master / Slave PIC OCW1 Master / Slave PIC OCW2 Master / Slave PIC OCW3 Master / Slave PIC Interrupt Request and Service Registers for OCW3 Commands Page 225 Page 225 Page 225 Page 225 Page 225 Page 225 Page 226 Page 226 Page 224 Page 224 Page 224 Page 224 Page 224 Page 224 Page 224
Keyboard Controller Registers (Table 4-31) 060h 061h 062h 064h 066h 092h R/W R/W R/W R/W R/W R/W External Keyboard Controller Data Register Port B Control Register External Keyboard Controller Mailbox Register External Keyboard Controller Command Register External Keyboard Controller Mailbox Register Port A Control Register Page 227 Page 227 Page 227 Page 227 Page 227 Page 227
Real Time Clock Registers (Table 4-32) 070h 071h WO R/W RTC Address Register RTC Data Register Page 227 Page 227
Miscellaneous Registers (Table 4-33) 170h-177h/ 376h 1F0h-1F7h/ 3F6h 4D0h 4D1h 121Ch-121Fh R/W R/W R/W R/W RO Secondary IDE Registers Primary IDE Registers Interrupt Edge/Level Select Register 1 Interrupt Edge/Level Select Register 2 ACPI Timer Count Register Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch. Otherwise use F1BAR+Offset 1Ch. Page 228 Page 228 Page 228 Page 228 Page 228
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Table 4-14. V-ACPI I/O Register Space Summary
ACPI_ BASE 00h-03h 04h 05h 06h 07h 08h-09h 0Ah-0Bh 0Ch-0Dh 0Eh-0Fh 10h-11h 12h-13h 14h-17h 18h-1Fh Type R/W RO -R/W -R/W R/W R/W R/W R/W R/W R/W -Align 4 1 1 1 1 2 2 4 2 2 2 4 Length 4 1 1 1 1 2 2 2 2 2 2 4 8 Name P_CNT: Processor Control Register P_LVL2: Enter C2 Power State Register Reserved SMI_CMD: OS/BIOS Requests Register (ACPI Enable/ Disable Port) Reserved PM1A_STS: PM1A Status Register PM1A_EN: PM1A Enable Register PM1A_CNT: PM1A Control Register SETUP_IDX: Setup Index Register (V-ACPI internal index register) GPE0_STS: General Purpose Event 0 Status Register GPE0_EN: General Purpose Event 0 Enable Register SETUP_DATA: Setup Data Register (V-ACPI internal data register) Reserved: For Future V-ACPI Implementations Reset Value 00000000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 0000h 00000000h -Reference (Table 4-34) Page 229 Page 229 Page 229 Page 229 Page 229 Page 230 Page 230 Page 230 Page 230 Page 231 Page 231 Page 232 Page 232
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4.3 CHIPSET REGISTER SPACE
4.3.1 Bridge Configuration Registers - Function 0 The register space designated as Function 0 (F0) contains registers used to configure features (e.g., power management) and functionality unique to the CS5530A. All registers in Function 0 are directly accessed (i.e., there are no memory or I/O mapped registers in F0). Table 4-15 gives the bit formats for these registers. The registers at F0 Index 50h-FFh can also be accessed at F1BAR+Memory Offset 50h-FFh. The preferred method is to program these registers through the F0 register space. If the F0 PCI Configuration Trap bit (F0 Index 41h[0]) is enabled and an access is attempted to any of the F0 PCI header and bridge configuration registers except F0 Index 40h-43h, an SMI is generated instead. The Chipset Register Space of the CS5530A is comprised of five separate functions (Function 0 through 4, F0-F4), each with its own register space and PCI header registers. F1-F4 have memory or I/O mapped registers from a Base Address Register (BAR). The PCI header registers in all functions are very similar. F0: F1: F2: F3: F4: Bridge Configuration Register Space SMI Status and ACPI Timer Register Space IDE Controller Register Space XpressAUDIO Subsystem Register Space Video Controller Register Space
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers
Bit Description Vendor Identification Register (RO) Reset Value = 1078h
Index 00h-01h 15:0
Vendor Identification Register (Read Only) Device Identification Register (RO) Reset Value = 0100h
Index 02h-03h 15:0
Device Identification Register (Read Only) PCI Command Register (R/W) Reset Value = 000Fh
Index 04h-05h 15:10 9 8 7 6 5 4 3 2 1 0 Reserved: Set to 0.
Fast Back-to-Back Enable (Read Only): This function is not supported when the CS5530A is a master. It is always disabled (always reads 0). SERR#: Allow SERR# assertion on detection of special errors. 0 = Disable (Default); 1 = Enable. Wait Cycle Control (Read Only): This function is not supported in the CS5530A. It is always disabled (always reads 0). Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when a parity error is detected. 0 = Disable (Default); 1 = Enable. VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530A. It is always disabled (always reads 0). Memory Write and Invalidate: Allow the CS5530A to do memory write and invalidate cycles, if the PCI Cache Line Size Register (F0 Index 0Ch) is set to 16 bytes (04h). 0 = Disable (Default); 1 = Enable. Special Cycles: Allow the CS5530A to respond to special cycles. 0 = Disable; 1 = Enable (Default). This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle. Bus Master: Allow the CS5530A bus mastering capabilities. 0 = Disable; 1 = Enable (Default). This bit must be set to 1. Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable (Default). I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Description PCI Status Register (R/W) Reset Value = 0280h
Index 06h-07h 15 14 13 Write 1 to clear.
Detected Parity Error: This bit is set whenever a parity error is detected. Signaled System Error: This bit is set whenever the CS5530A asserts SERR# active. Write 1 to clear. Received Master Abort: This bit is set whenever a master abort cycle occurs while the CS5530A is the master. A master abort occurs when a PCI cycle is not claimed, except for special cycles. Write 1 to clear. Received Target Abort: This bit is set whenever a target abort is received while the CS5530A is the master for the PCI cycle. Write 1 to clear. Signaled Target Abort: This bit is set whenever the CS5530A signals a target abort. This occurs when an address parity error occurs for an address that hits in the active address decode space of the CS5530A. Write 1 to clear. DEVSEL# Timing (Read Only): These bits are always 01, as the CS5530A always responds to cycles for which it is an active target with medium DEVSEL# timing. 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved Data Parity Detected: This bit is set when: 1) The CS5530A asserted PERR# or observed PERR# asserted. 2) The CS5530A is the master for the cycle in which a parity error occurred and the Parity Error bit is set (F0 Index 04h[6] = 1). Write 1 to clear.
12
11
10:9 8
7
Fast Back-to-Back Capable (Read Only): As a target, the CS5530A is capable of accepting fast back-to-back transactions. 0 = Disable; 1 = Enable. This bit is always set to 1. Reserved: Set to 0. Device Revision ID Register (RO) Device Revision ID (Read Only): Device revision level. 20h for revision A; 30h for revision B. PCI Class Code Register (RO) PCI Cache Line Size Register (R/W) Reset Value = 060100h Reset Value = 00h Reset Value = xxh
6:0 Index 08h 7:0
Index 09h-0Bh Index 0Ch 7:0
PCI Cache Line Size Register: This register sets the size of the PCI cache line, in increments of four bytes. For memory write and invalidate cycles, the PCI cache line size must be set to 16 bytes (04h), and the Memory Write and Invalidate bit must be set (F0 Index 04h[4] = 1). PCI Latency Timer Register (R/W) Reserved: Set to 0. PCI Latency Timer Value: The PCI Latency Timer Register prevents system lockup when a slave does not respond to a cycle that the CS5530A masters. If the value is set to 00h (default), the timer is disabled. If the timer is written with any other value, bits [3:0] become the four most significant bytes in a timer that counts PCI clocks for slave response. The timer is reset on each valid data transfer. If the timer expires before the next assertion of TRDY# is received, the CS5530A stops the transaction with a master abort and asserts SERR#, if enabled to do so (F0 Index 04h[8] = 1). PCI Header Type Register (RO) Reset Value = 80h Reset Value = 00h
Index 0Dh 7:4 3:0
Index 0Eh 7:0 Index 0Fh 7 6 5:4 3:0
PCI Header Type Register (Read Only): This register defines the format of this header. This header is of type format 0. Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0). PCI BIST Register (RO) BIST Capable (Read Only): Is device capable of running a built-in self-test (BIST)? 0 = No; 1 = Yes, Start BIST: Setting this bit to a one starts up a BIST on the device. The device resets this bit when the BIST has been completed. (Not supported.) Reserved (Read Only) BIST Completion Code (Read Only): Upon completion of the BIST, the completion code is stored in these bits. A completion code of zero indicates the BIST has successfully been completed. All other values indicate some type of BIST failure. Reserved Reserved Reset Value = xxh 00h Reset Value = 00h
Index 10h-1Fh Index 20h-3Fh
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 40h 7 6 5 4 3 2:1 0 Description PCI Function Control Register 1 (R/W) Reset Value = 89h
PCI Interrupt Acknowledge Cycle Response: Allow the CS5530A responds to PCI interrupt acknowledge cycles. 0 = Disable; 1 = Enable. Single Write Mode: The CS5530A accepts only single cycle write transfers as a slave on the PCI bus and performs a target disconnect with the first data transferred. 0 = Disable (accepts burst write cycles); 1 = Enable. Single Read Mode: The CS5530A accepts only single cycle read transfers as a slave on the PCI bus and performs a target disconnect with the first data transferred. 0 = Disable (accepts burst read cycles); 1 = Enable. Retry PCI Cycles: Retry inbound PCI cycles if data is buffered and waiting to go outbound on PCI. 0 = No Retry; 1 = Retry. Write Buffer: PCI slave write buffer. 0 = Disable; 1 = Enable. Reserved: Set to 0. BS8/16: This bit can not be written. Always = 1.
Note: Bits 6 and 5 emulate the behavior of first generation SIO devices developed for PCI. They should normally remain cleared. Index 41h 7 6 PCI Function Control Register 2 (R/W) Reset Value = 10h
Burst to Beat: If this bit is set to 1, the CS5530A performs a single access from the PCI bus. If set to 0, burst accesses are enabled. F2 IDE Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access is attempted to one of the F2 PCI header registers, an SMI is generated instead. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5].
5 4 3
PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530A (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system). 0 = Disable; 1 = Enable. Write Buffer Enable: Allow 16-byte buffering for X-Bus to PCI bus writes. 0 = Disable; 1 = Enable. F1 Power Management Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the F1 PCI configuration header registers, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5].
2:1
Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another device. The CS5530A defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode
0
F0 PCI Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access is attempted to any of the F0 PCI header registers except F0 Index 40h-43h, an SMI is generated instead. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5].
Index 42h 7 6 5 4 3 2
PCI Function Control Register 3 (R/W) USB SMI I/O Configuration: Route USB-generated SMI to SMI# pin. 0 = Disable; 1 = Enable, USB-generated SMI pulls SMI# pin active (low).
Reset Value = ACh
USB SMI Power Mgmnt Configuration: Route USB-generated SMI to Top Level SMI Status Register, F1BAR+Memory Offset 00h/02h[14]. 0 = Disable; 1 = Enable. Delayed Transactions: Allow delayed transactions on the PCI bus. 0 = Disable; 1 = Enable. Also see F0 Index 43h[1]. DMA Priority: Allow USB DMA to have priority over other DMA requests. 0 = Disable; 1 = Enable. No X-Bus ARB, Buffer Enable: When the CS5530A is a PCI target, allow buffering of PCI transactions without X-Bus arbitration. 0 = Disable; 1 = Enable. HOLD_REQ# (Pin H26): HOLD_REQ# signal (pin H26). 0 = Disable; 1 = Enable. Note: Although the HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., enabled, set to 1) for non-preemptive arbitration to operate correctly.
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit 1 Description F4 Video Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access is attempted to one of the F4 PCI header registers, an SMI is generated instead. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 0 F3 Audio Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access is attempted to one of the F3 PCI header registers, an SMI is generated instead. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. Index 43h 7 6 5 4 3 2 1 Reserved: Set to 0. Enable SA20: Pin AD22 configuration. 0 = GPIO4; 1 = SA20. If bit 6 or bit 2 is set to 1, then pin AD22 = SA20. Legacy Cycles Assert HOLD_REQ#: Allow legacy cycles to cause HOLD_REQ# to be asserted. 0 = Disable; 1 = Enable. Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disable). Read Cycles Assert HOLD_REQ#: Allow read cycles to cause HOLD_REQ# to be asserted. 0 = Disable; 1 = Enable. Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disable). Any Cycle Asserts HOLD_REQ#: Allow any cycle to cause HOLD_REQ# to be asserted. 0 = Disable; 1 = Enable. Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disable). Enable SA[23:20]: Pins AF23, AE23, AC21, and AD22 configuration. 0 = GPIO[7:4]; 1 = SA[23:20]. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. PCI Retry Cycles: When the CS5530A is a PCI target and the PCI buffer is not empty, allow the PCI bus to retry cycles. 0 = Disable; 1 = Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid. 0 Index 44h 7 USB Core: 0 = Disable; 1 = Enable. Reset Control Register (R/W) ISA Mode: This bit is set to read back the strap value of the INTR pin (pin P26) during POR. 0 = ISA Limited; 1 = ISA Master. This bit can be written after POR# deasserts to change the ISA mode selected. However, writing to this bit is not recommended due to the actual strapping done on the board. 6 IDSEL Mode: This bit is set to read back the strap value of the HOLD_REQ# pin (pin H26) during POR. 0 = AD28 is IDSEL for Chipset Register Space and AD29 is IDSEL for USB Register Space; 1 = AD26 is IDSEL for Chipset Register Space and AD27 is IDSEL for USB Register Space. This bit can be written after POR# deasserts to change the IDSEL settings. However, writing to this bit is not recommended due to the actual strapping done on the board. 5:4 Clock 32K Control: Controls the source of the CLK_32K pin (AE3). 00 = CLK_32K is internally derived from CLK_14MHZ (pin P24) and is not output on pin AE3 (Default) 01 = CLK_32K is internally derived from CLK_14MHZ (pin P24) and is output on pin AE3 10 = CLK_32K is an input 11 = Invalid IDE Controller Reset: Reset both of the CS5530A IDE controllers' internal state machines. 0 = Run; 1 = Reset. This bit is level-sensitive and must be explicitly cleared to 0 to remove the reset. 2 1 IDE Reset: Reset IDE bus. 0 = Deassert IDE bus reset signal; 1 = Assert IDE bus reset signal. This bit is level-sensitive and must be explicitly cleared to 0 to remove the reset. PCI Reset: Reset PCI bus. 0 = Disable; 1 = Enable. When set, the CS5530A PCI_RST# output signal (pin C14) is asserted and all devices on the PCI bus including PCIUSB are reset. No other function within the CS5530A is affected by this bit. It does not reset PCI registers. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. 0 X-Bus Warm Start: Reading and writing this bit has two different meanings/functions. Reading this bit: Has a warm start occurred since power-up? 0 = Yes; 1 = No Writing this bit: 0 = NOP; 1 = Execute system wide reset (used only for clock configuration at power-up). Note: X-Bus warm start will toggle the CPU_RST and PCI_RST# lines. Index 45h-4Fh Reserved Reset Value = 00h Reset Value = 01h USB Shadow Register (R/W) Reset Value = 03h
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 50h 7 6 5 4 3 2:0 Description PIT Control/ISA CLK Divider (R/W) PIT Software Reset: 0 = Disable; 1 = Enable. PIT Counter 1: 0 = Forces Counter 1 output (OUT1) to zero; 1 = Allows Counter 1 output (OUT1) to pass to I/O Port 061h[4]. PIT Counter 1 Enable: 0 = Sets GATE1 input low; 1 = Sets GATE1 input high. PIT Counter 0: 0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0. PIT Counter 0 Enable: 0 = Sets GATE0 input low; 1 = Sets GATE0 input high. ISA Clock Divisor: Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for approximately 8 MHz. 000 = Reserved 001 = Divide by two 010 = Divide by three 011 = Divide by four Index 51h 7:4 100 = Divide by five 101 = Divide by six 110 = Divide by seven 111 = Divide by eight ISA I/O Recovery Control Register (R/W) Reset Value = 40h Reset Value = 7Bh
If 25 MHz PCI clock, use setting of 010 (divide by 3). If 30 or 33 MHz PCI clock, use a setting of 011 (divide by 4).
8-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 ISA clock 0001 = 2 ISA clocks 0010 = 3 ISA clocks 0011 = 4 ISA clocks 0100 = 5 ISA clocks 0101 = 6 ISA clocks 0110 = 7 ISA clocks 0111 = 8 ISA clocks 1000 = 9 ISA clocks 1001 = 10 ISA clocks 1010 = 11 ISA clocks 1011 = 12 ISA clocks 1100 = 13 ISA clocks 1101 = 14 ISA clocks 1110 = 15 ISA clocks 1111 = 16 ISA clocks
3:0
16-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This count is in addition to a preset one-clock delay built into the controller. 0000 = 1 ISA clock 0001 = 2 ISA clocks 0010 = 3 ISA clocks 0011 = 4 ISA clocks 0100 = 5 ISA clocks 0101 = 6 ISA clocks 0110 = 7 ISA clocks 0111 = 8 ISA clocks 1000 = 9 ISA clocks 1001 = 10 ISA clocks 1010 = 11 ISA clocks 1011 = 12 ISA clocks 1100 = 13 ISA clocks 1101 = 14 ISA clocks 1110 = 15 ISA clocks 1111 = 16 ISA clocks Reset Value = F8h
Index 52h 7
ROM/AT Logic Control Register (R/W)
Snoop Fast Keyboard Gate A20 and Fast Reset: Enables the snoop logic associated with keyboard commands for A20 Mask and Reset. 0 = Disable; 1 = Enable (snooping). If disabled, the keyboard controller handles the commands. Game Port GPORT_CS# on Writes: Allow GPORT_CS# to be asserted for writes to the game port (I/O Port 200h and 201h). 0 = Disable; 1 = Enable. Game Port GPORT_CS# on Reads: Allow GPORT_CS# to be asserted for reads to the game port (I/O Port 200h and 201h). 0 = Disable; 1 = Enable. Enable A20M# Deassertion on Warm Reset: Force A20M# high during a Warm Reset (guarantees that A20M# is deasserted regardless of the state of A20). 0 = Disable; 1 = Enable. Enable I/O Port 092h Decode (Port A): I/O Port 092h decode and the logical functions. 0 = Disable; 1 = Enable. Upper ROM Address Range: KBROMCS# is asserted for ISA memory read accesses. 0 = FFFC0000h-FFFFFFFFh (256 KB, Default); 1 = FF000000h-FFFFFFFFh (16 MB) Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). ROM Write Enable: Assert KBROMCS# during writes to configured ROM space (configured in bits 2 and 0), allowing Flash programming. 0 = Disable; 1 = Enable. Lower ROM Address Range: KBROMCS# is asserted for ISA memory read accesses. 0 = 000F0000h-000FFFFFh (64 KB, Default); 1 = 000E0000h-000FFFFFh (128 KB). Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]). Alternate CPU Support Register (R/W) Reserved: Set to 0. Game Port Write Blocks ISA: Block ISA cycle on game port (I/O Port 200h and 201h) write. 0 = Disable; 1 = Enable. Bidirectional SMI Enable: 0 = Disable; 1 = Enable. This bit must be set to 0. Game Port Read Block ISA: Block ISA cycle on game port (I/O Port 200h and 201h) read. 0 = Disable; 1 = Enable. Reset Value = 00h
6 5 4 3 2
1 0
Index 53h 7 6 5 4
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit 3 Description Game Port Write SMI: Allow SMI generation on writes to game port (I/O Port 200h and 201h). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 84h/F4h[4]. For "Game Port Read SMI", see F0 Index 83h[4]. 2 RTC Enable/RTC Pin Configuration: 0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled; 1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled. Note: The RTC Index Shadow Register (F0 Index BBh) is independent of the setting of this bit. 1 0 Reserved: Set to 1 after register reset. Failure to do this leaves IRQ13 in an unsupported mode. Generate SMI on A20M# toggle: 0 = Disable; 1 = Enable. This bit must be set to 1. SMI status is reported in F1BAR+Memory Offset 00h/02h[7] (only). Index 54h-59h Index 5Ah 7 6 5 4 3 2 1 0 Reserved Decode Control Register 1 (R/W) Reset Value = xxh Reset Value = 03h
Secondary Floppy Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 372h, 373h, 375h, and 377h. 0 = Subtractive; 1 = Positive. Primary Floppy Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3F2h, 3F4h, 3F5h, and 3F7h. 0 = Subtractive; 1 = Positive. COM4 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 2E8h-2EFh. 0 = Subtractive; 1 = Positive. COM3 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3E8h-3EFh. 0 = Subtractive; 1 = Positive. COM2 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 2F8h-2FFh. 0 = Subtractive; 1 = Positive. COM1 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3F8h-3FFh. 0 = Subtractive; 1 = Positive. Keyboard Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 060h and 064h (and 062h/066h if enabled). 0 = Subtractive; 1 = Positive. Real Time Clock Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 070h-7Fh. 0 = Subtractive; 1 = Positive.
Note: Positive decoding by the CS5530A speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530A. It is assumed that if positive decode is enabled, the port exists on the ISA bus. Index 5Bh 7 6 5 Decode Control Register 2 (R/W) Reset Value = 20h
Keyboard I/O Port 062h/066h Decode: This alternate port to the keyboard controller is provided in support of the 8051SL notebook keyboard controller mailbox. 0 = Disable; 1 = Enable. Reserved: Set to 0. BIOS ROM Positive Decode: Selects PCI positive or subtractive decoding for accesses to the configured ROM space. 0 = Subtractive; 1 = Positive. ROM configuration is at F0 Index 52h[2:0]. Secondary IDE Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 170h177h and 376h. 0 = Subtractive; 1 = Positive. Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA bus. Primary IDE Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 1F0h-1F7h and 3F6h. 0 = Subtractive; 1 = Positive. Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA bus. LPT3 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 278h-27Fh. 0 = Subtractive; 1 = Positive. This bit does not affect 7BCh-7BEh, which is always decoded subtractively. LPT2 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 378h-37Fh. 0 = Subtractive; 1 = Positive. This bit does not affect 678h-67Ah, which is always decoded subtractively. LPT1 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3BCh-3BFh. 0 = Subtractive; 1 = Positive. This bit does not affect 778h-77Ah, which is always decoded subtractively.
4
3
2
1
0
Note: Positive decoding by the CS5530A speeds up the I/O cycle time. The keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in the CS5530A. It is assumed that if positive decode is enabled, the port exists on the ISA bus. www.national.com 158 Revision 1.1
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 5Ch 7:4 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 3:0 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 Description PCI Interrupt Steering Register 1 (R/W) INTB# Target Interrupt: Selects target interrupt for INTB#. 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 ` 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 Reset Value = 00h
INTA# Target Interrupt: Selects target interrupt for INTA#.
Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. Index 5Dh 7:4 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 3:0 0000 = Disable 0001 = IRQ1 0010 = RSVD 0011 = IRQ3 PCI Interrupt Steering Register 2 (R/W) INTD# Target Interrupt: Selects target interrupt for INTD#. 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1000 = RSVD 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 1100 = IRQ12 1101 = RSVD 1110 = IRQ14 1111 = IRQ15 Reset Value = 00h
INTC# Target Interrupt: Selects target interrupt for INTC#.
Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. Index 5Eh-6Fh Index 70h-71h 15:0 Reserved General Purpose Chip Select Base Address Register (R/W) Reset Value = xxh Reset Value = 0000h
General Purpose Chip Select I/O Base Address: This 16-bit value represents the I/O base address used to enable the assertion of the GPCS# signal. This register, together with General Purpose Chip Select Control Register (F0 Index 72h) is used to configure the operation of the GPCS# pin.
Index 72h 7 6 5 4:0
General Purpose Chip Select Control Register (R/W) General Purpose Chip Select: GPCS# (pin AF26). 0 = Disable; 1 = Enable. If the GPCS# signal is disabled (i.e., this bit = 0) its output is permanently driven high.
Reset Value = 00h
Writes Result in Chip Select: Writes to configured I/O address (base address configured in F0 Index 70h and range configured in bits [4:0]) causes GPCS# signal to be asserted. 0 = Disable; 1 = Enable. Reads Result in Chip Select: Reads from configured I/O address (base address configured in F0 Index 70h and range configured in bits [4:0]) causes GPCS# signal to be asserted. 0 = Disable; 1 = Enable. General Purpose Chip Select I/O Address Range: This 5-bit field selects the range of GPCS# signal. 00000 = 1 byte 01111 = 16 bytes 00001 = 2 bytes 11111 = 32 bytes 00011 = 4 bytes All other combinations are reserved. 00111 = 8 bytes
Note: This register, together with General Purpose Chip Select Base Address Register (F0 Index 70h) is used to configure the operation of the GPCS# pin. Index 73h-7Fh Reserved Reset Value = xxh
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 80h 7:6 5 Reserved: Set to 0. Codec SDATA_IN SMI: Allow AC97 codec to generate an SMI due to codec producing a positive edge on SDATA_IN. 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[2]. 4 Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GX-series processor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power managed using CPU Suspend modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an external VGA access (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) on the PCI bus is also supported. This configuration is nonstandard, but it does allow the power management routines to support an external VGA chip. 3 IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power managed using CPU Suspend modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch). 2 1 Traps: Globally enable all power management device I/O traps. 0 = Disable; 1 = Enable. This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h. Idle Timers: Globally enable all power management device idle timers. 0 = Disable; 1 = Enable. Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts. This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h), nor on the General Purpose (UDEFx) Timers (F0 Index 88h-8Bh). This bit must be set for the command to trigger the SUSP#/SUSPA# feature to function (see F0 Index AEh). 0 Power Management: Global power management. 0 = Disable; 1 = Enabled. This bit must be set (1) immediately after POST for some power management resources to function. Until this is done, the command to trigger the SUSP#/SUSPA# feature is disabled (see F0 Index AEh) and all SMI# trigger events listed for F0 Index 84h-87h are disabled. A `0' in this bit does NOT stop the Idle Timers if bit 1 of this register is a `1', but only prevents them from generating an SMI# interrupt. It also has no effect on the UDEF traps. Description Power Management Enable Register 1 (R/W) Reset Value = 00h
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 81h 7 Description Power Management Enable Register 2 (R/W) Reset Value = 00h
Video Access Idle Timer Enable: Load timer from Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the video address range (sets bit 0 of the GX-series processor's PSERIAL register) the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7].
6
User Defined Device 3 (UDEF3) Idle Timer Enable: Load timer from UDEF3 Idle Timer Count Register (F0 Index A4h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6].
5
User Defined Device 2 (UDEF2) Idle Timer Enable: Load timer from UDEF2 Idle Timer Count Register (F0 Index A2h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5].
4
User Defined Device 1 (UDEF1) Idle Timer Enable: Load timer from UDEF1 Idle Timer Count Register (F0 Index A0h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the programmed address range the timer is reloaded with the programmed count. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4].
3
Keyboard/Mouse Idle Timer Enable: Load timer from Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3].
2
Parallel/Serial Idle Timer Enable: Load timer from Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2].
1
Floppy Disk Idle Timer Enable: Load timer from Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count. Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, and 3F7 Secondary floppy disk: I/O Port 372h, 373h, 375h, and 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1].
0
Primary Hard Disk Idle Timer Enable: Load timer from Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0].
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 82h 7 Description Power Management Enable Register 3 (R/W) Video Access Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX-series processor's PSERIAL register) an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[7]. 6 User Defined Device 3 (UDEF3) Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[4]. 5 User Defined Device 2 (UDEF2) Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[3]. 4 User Defined Device 1 (UDEF1) Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF1 address programming is at F0 Index C0h (base address register), and CCh (control register). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[2]. 3 Keyboard/Mouse Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[3]. 2 Parallel/Serial Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[2]. 1 Floppy Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated. Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, or 3F7 Secondary floppy disk: I/O Port 372h, 373h, 375h, or 377h Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[1]. 0 Primary Hard Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[0]. Reset Value = 00h
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 83h 7 Description Power Management Enable Register 4 (R/W) Reset Value = 00h
Secondary Hard Disk Idle Timer Enable: Load timer from Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4].
6
Secondary Hard Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[5].
5
ACPI Timer SMI: Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0].
4
Game Port Read SMI: Allow SMI generation on reads to game port (I/O Port 200h and 201h). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 84h/F4h[4]. For "Game Port Write SMI" see F0 Index 53h[3].
3
VGA Timer Enable: Turn on VGA Timer and generate an SMI when the timer reaches 0. 0 = Disable; 1 = Enable. VGA Timer programming is at F0 Index 8Eh and F0 Index 8Bh[6]. To reload the count in the VGA timer, disable it, optionally change the count value in F0 Index 8Eh[7:0], and reenable it before enabling power management. SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only). Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. The VGA Timer counts whether power management is enabled or disabled.
2
Video Retrace Interrupt SMI: Allow SMI generation whenever video retrace occurs. 0 = Disable; 1 = Enable. This information is decoded from the serial connection (PSERIAL register, bit 7) from the GX-series processor. This function is normally not used for power management but for softVGA routines. SMI status reporting is at F1BAR+Memory Offset 00h/02h[5] (only).
1
General Purpose Timer 2 (GP Timer 2) Enable: Turn on GP Timer 2 and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index 8Ah and 8Bh[5,3,2]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[1].
0
General Purpose Timer 1 (GP Timer 1) Enable: Turn on GP Timer 1 and generate an SMI when the timer expires. 0 = Disable; 1 = Enable. This idle timer's load is multi-sourced and is reloaded any time an enabled event (F0 Index 89h[6:0]) occurs. GP Timer 1 programming is at F0 Index 88h and 8Bh[4]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0]
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 84h 7:5 4 Reserved Game Port SMI Status (Read Only): SMI was caused by R/W access to game port (I/O Port 200h and 201h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. Game Port Read SMI generation enabling is at F0 Index 83h[4]. Game Port Write SMI generation enabling is at F0 Index 53h[3]. 3 GPIO7 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO7 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[3]. 2 GPIO5 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO5 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[2]. 1 GPIO4 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO4 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[1]. 0 GPIO3 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO3 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[0]. Note: Properly-configured means that the GPIO pin must be enabled as a GPIO (if multiplexed pin), as an input, and to cause an SMI. This register provides status on various power management SMI events to the SMI handler. It is called a Mirror register since an identical register exists at F0 Index F4h. Reading this register does not clear the status, while reading its counterpart at F0 Index F4h does clear the status. Description Second Level Power Management Status Mirror Register 1 (RO) Reset Value = 00h
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 85h 7 Description Second Level Power Management Status Mirror Register 2 (RO) Reset Value = 00h
Video Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Video Idle Timer Count Register (F0 Index A6h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[7].
6
User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read Only): SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[6].
5
User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read Only): SMI was caused by expiration of the UDEF2 Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[5].
4
User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read Only): SMI was caused by expiration of the UDEF1 Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[4].
3
Keyboard/Mouse Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[3].
2
Parallel/Serial Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[2].
1
Floppy Disk Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Floppy Disk Idle Timer Count Register (F0 Index 9Ah)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[1].
0
Primary Hard Disk Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Primary Hard Disk Idle Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[0].
Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the duration configured in the Idle Timer Count register for that device, causing an SMI. It is called a Mirror register since an identical register exists at F0 Index F5h. Reading this register does not clear the status, while reading its counterpart at F0 Index F5h does clear the status.
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 86h 7 Description Second Level Power Management Status Mirror Register 3 (RO) Reset Value = 00h
Video Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the Video I/O Trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[7].
6 5
Reserved (Read Only) Secondary Hard Disk Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the secondary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[6].
4
Secondary Hard Disk Idle Timer SMI Status (Read Only): SMI was caused by expiration of Hard Disk Idle Timer Count Register (F0 Index ACh)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[7].
3
Keyboard/Mouse Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the keyboard or mouse? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[3].
2
Parallel/Serial Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to either the serial or parallel ports? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[2].
1
Floppy Disk Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the floppy disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[1].
0
Primary Hard Disk Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the primary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[0].
Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the device while the trap was enabled, causing an SMI. It is called a Mirror register since an identical register exists at F0 Index F6h. Reading this register does not clear the status, while reading its counterpart at F0 Index F6h does clear the status.
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 87h 7 Description Second Level Power Management Status Mirror Register 4 (RO) Reset Value = 00h
GPIO2 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO2 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[2].
6
GPIO1 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO1 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[1].
5
GPIO0 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO0 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[0].
4 3
Lid Position (Read Only): This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid switch indicator, this bit reflects the state of the pin. Lid Switch SMI Status (Read Only): SMI was caused by a transition on the GPIO6 (lid switch) pin? 0 = No; 1 = Yes. For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index 92h[6] =1).
2
Codec SDATA_IN SMI Status (Read Only): SMI was caused by AC97 codec producing a positive edge on SDATA_IN? 0 = No; 1 = Yes. This is the second level of status is reporting. The top level status is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 80h[5].
1
RTC Alarm (IRQ8) SMI Status (Read Only): SMI was caused by an RTC interrupt? 0 = No; 1 = Yes. This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].
0
ACPI Timer SMI Status (Read Only): SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation configuration is at F0 Index 83h[5].
Note: Properly-configured means that the GPIO pin must be enabled as a GPIO (if multiplexed pin), an input, and to cause an SMI. This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. It is called a Mirror register since an identical register exists at F0 Index F7h. Reading this register does not clear the status, while reading its counterpart at F0 Index F7h does clear the status. Index 88h 7:0 General Purpose Timer 1 Count Register (R/W) Reset Value = 00h
General Purpose Timer 1 Count: This register holds the load value for GP Timer 1. This value can represent either an 8bit or 16-bit timer (selected at F0 Index 8Bh[4]). It is loaded into the timer when the timer is enabled (F0 Index 83h[0] =1). Once enabled, an enabled event (configured in F0 Index 89h[6:0]) reloads the timer. The timer is decremented with each clock of the configured timebase. Upon expiration of the timer, an SMI is generated and the top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. The second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0]). Once expired, this timer must be re-initialized by either disabling and enabling it, or writing a new count value here. This timer's timebase can be configured as 1 msec or 1 sec at F0 Index 89h[7].
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 89h 7 6 Description General Purpose Timer 1 Control Register (R/W) Reset Value = 00h
Timebase for General Purpose Timer 1: Selects timebase for GP Timer 1 (F0 Index 88h). 0 = 1 sec; 1 = 1 msec. Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity: 0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF3 reloads GP Timer 1. UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register).
5
Re-trigger General Purpose Timer 1 on User Defined Device 2 (UDEF2) Activity: 0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF2 reloads GP Timer 1. UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register).
4
Re-trigger General Purpose Timer 1 on User Defined Device 1 (UDEF1) Activity: 0 = Disable; 1 = Enable. Any access to the configured (memory or I/O) address range for UDEF1 reloads GP Timer 1. UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register)
3
Re-trigger General Purpose Timer 1 on Keyboard or Mouse Activity: 0 = Disable; 1 = Enable Any access to the keyboard or mouse I/O address range (listed below) reloads GP Timer 1. Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)
2
Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity: 0 = Disable; 1 = Enable. Any access to the parallel or serial port I/O address range (listed below) reloads the GP Timer 1. LPT1: I/O Port 378h-37Fh, 778h-77Ah LPT2: I/O Port 278h-27Fh, 678h-67Ah COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded) COM3: I/O Port 3E8h-3EFh COM4: I/O Port 2E8h-2EFh
1
Re-trigger General Purpose Timer 1 on Floppy Disk Activity: 0 = Disable; 1 = Enable. Any access to the floppy disk drive address ranges (listed below) reloads GP Timer 1. Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, and 3F7 Secondary floppy disk: I/O Port 372h, 373h, 375h, and 377h The active floppy drive is configured via F0 Index 93h[7].
0 Index 8Ah 7:0
Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity: 0 = Disable; 1 = Enable. Any access to the primary hard disk drive address range selected in F0 Index 93h[5] reloads GP Timer 1. General Purpose Timer 2 Count Register (R/W) Reset Value = 00h
General Purpose Timer 2 Count: This register holds the load value for GP Timer 2. This value can represent either an 8bit or 16-bit timer (configured in F0 Index 8Bh[5]). It is loaded into the timer when the timer is enabled (F0 Index 83h[1] = 1). Once the timer is enabled and a transition occurs on GPIO7, the timer is re-loaded. The timer is decremented with each clock of the configured timebase. Upon expiration of the timer, an SMI is generated and the top level of status is F1BAR+Memory Offset 00h/02h[9] and the second level of status is reported in F1BAR+Memory Offset 04h/06h[1]). Once expired, this timer must be re-initialized by either disabling and enabling it, or writing a new count value here. For GPIO7 to act as the reload for this timer, it must be enabled as such (F0 Index 8Bh[2]) and be configured as an input (F0 Index 90h[7]). This timer's timebase can be configured as 1 msec or 1 sec in F0 Index 8Bh[3].
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 8Bh 7 6 5 Description General Purpose Timer 2 Control Register (R/W) Re-trigger General Purpose Timer 1 on Secondary Hard Disk Activity: 0 = Disable; 1 = Enable. Any access to the secondary hard disk drive address range selected in F0 Index 93h[4] reloads GP Timer 1. VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh). 0 = 1 ms; 1 = 32 s. General Purpose Timer 2 Shift: GP Timer 2 is treated as an 8-bit or 16-bit timer. 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah). As a 16-bit timer, the value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 2. 4 General Purpose Timer 1 Shift: GP Timer 1 is treated as an 8-bit or 16-bit timer. 0 = 8-bit; 1 = 16-bit. As an 8-bit timer, the count value is that loaded into GP Timer 1 Count Register (F0 Index 88h). As a 16-bit timer, the value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become zero, and this 16-bit value is used as the count for GP Timer 1. 3 2 Timebase for General Purpose Timer 2: Selects timebase for GP Timer 2 (F0 Index 8Ah). 0 = 1 sec; 1 = 1 msec. Re-trigger General Purpose Timer 2 on GPIO7 Pin Transition: A configured transition on the GPIO7 pin reloads GP Timer 2 (F0 Index 8Ah). 0 = Disable; 1 = Enable. F0 Index 92h[7] selects whether a rising- or a falling-edge transition acts as a reload. For GPIO7 to work here, it must first be configured as an input (F0 Index 90h[7] = 0). 1:0 Index 8Ch 7:0 Reserved: Set to 0. IRQ Speedup Timer Count Register (R/W) Reset Value = 00h Reset Value = 00h
IRQ Speedup Timer Count: This register holds the load value for the IRQ speedup timer. It is loaded into the timer when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer's timebase is 1 ms. This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical value here would be 2 to 4 ms.
Index 8Dh 7:0
Video Speedup Timer Count Register (R/W)
Reset Value = 00h
Video Speedup Timer Count: This register holds the load value for the Video speedup timer. It is loaded into the timer when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and any access to the graphics controller occurs. When a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The video speedup timer's timebase is 1 ms. This speedup mechanism allows instantaneous response to video activity for full speed during video processing calculations. A typical value here would be 50 to 100 ms.
Index 8Eh 7:0
VGA Timer Count Register (R/W)
Reset Value = 00h
VGA Timer Load Value: This register holds the load value for the VGA timer. The value is loaded into the timer when the timer is enabled (F0 Index 83h[3] = 1). The timer is decremented with each clock of the configured timebase (F0 Index 8Bh[6]). Upon expiration of the timer, an SMI is generated and the status is reported in F1BAR+Memory Offset 00h/02h[6] (only). Once expired, this timer must be re-initialized by disabling it (F0 Index 83h[3] = 0) and then enabling it (F0 Index 83h[3] = 1). When the count value is changed in this register, the timer must be re-initialized in order for the new value to be loaded. This timer's timebase is selectable as 1 ms (default) or 32 s. (F0 Index 8Bh). Note: Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. It is not affected by the Global Power Management Enable setting at F0 Index 80h[0].
Index 8Fh
Reserved
Reset Value = xxh
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 90h 7 6 5 4 3 2 1 0 Description GPIO Pin Direction Register 1 (R/W) GPIO7 Direction: Selects if GPIO7 is an input or output. 0 = Input; 1 = Output. GPIO6 Direction: Selects if GPIO6 is an input or output. 0 = Input; 1 = Output. GPIO5 Direction: Selects if GPIO5 is an input or output. 0 = Input; 1 = Output. GPIO4 Direction: Selects if GPIO4 is an input or output. 0 = Input; 1 = Output. GPIO3 Direction: Selects if GPIO3 is an input or output. 0 = Input; 1 = Output. GPIO2 Direction: Selects if GPIO2 is an input or output. 0 = Input; 1 = Output. GPIO1 Direction: Selects if GPIO1 is an input or output. 0 = Input; 1 = Output. GPIO0 Direction: Selects if GPIO0 is an input or output. 0 = Input; 1 = Output. Reset Value = 00h
Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins' use as the alternate function. Index 91h 7 6 5 4 3 2 1 0 GPIO Pin Data Register 1 (R/W) GPIO7 Data: Reflects the level of GPIO7. 0 = Low; 1 = High. GPIO6 Data: Reflects the level of GPIO6. 0 = Low; 1 = High. GPIO5 Data: Reflects the level of GPIO5. 0 = Low; 1 = High. GPIO4 Data: Reflects the level of GPIO4. 0 = Low; 1 = High. GPIO3 Data: Reflects the level of GPIO3. 0 = Low; 1 = High. GPIO2 Data: Reflects the level of GPIO2. 0 = Low; 1 = High. GPIO1 Data: Reflects the level of GPIO1. 0 = Low; 1 = High. GPIO0 Data: Reflects the level of GPIO0. 0 = Low; 1 = High. Reset Value = 00h
Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from this register read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h. Index 92h 7 6 GPIO Control Register 1 (R/W) Reset Value = 00h
GPIO7 Edge Sense for Reload of General Purpose Timer 2: Selects which edge transition of GPIO7 causes GP Timer 2 to reload. 0 = Rising; 1 = Falling (Note 2). GPIO6 Enabled as Lid Switch: Allow GPIO6 to act as the lid switch input. 0 = GPIO6; 1 = Lid switch. When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI. The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[3]. If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid's position.
5 4 3 2
GPIO2 Edge Sense for SMI: Selects which edge transition of the GPIO2 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. GPIO1 Edge Sense for SMI: Selects which edge transition of the GPIO1 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. GPIO0 Edge Sense for SMI: Selects which edge transition of the GPIO0 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. Enable GPIO2 as an External SMI Source: Allow GPIO2 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[7].
1
Enable GPIO1 as an External SMI Source: Allow GPIO1 to be an external SMI source and generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 4). 0 = Disable; 1 = Enable (Note 3). Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[6].
0
Enable GPIO0 as an External SMI Source: Allow GPIO0 to be an external SMI source and generate an SMI on either a rising or falling edge transition (depends upon setting of bit 3). 0 = Disable; 1 = Enable (Note 3) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 87h/F7h[5].
Notes: 1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). 2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both. 3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the system from Suspend when the clocks are stopped.
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 93h 7 6 5 Description Miscellaneous Device Control Register (R/W) Reset Value = 00h
Floppy Drive Port Select: All system resources used to power manage the floppy drive use the primary or secondary FDC addresses for decode. 0 = Primary; 1 = Primary and Secondary. Reserved: This bit must always be set to 1. Partial Primary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as primary hard disk accesses. 0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h 1 = Power management monitors only writes to I/O Port 1F6h and 1F7h
4
Partial Secondary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as secondary hard Disk accesses. 0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h 1 = Power management monitors only writes to I/O Port 176h and 177h
3:2 1 0
Reserved: Set to 0. Mouse on Serial Enable: Mouse is present on a serial port. 0 = No; 1 = Yes. (Note) Mouse Port Select: Selects which serial port the mouse is attached to. 0 = COM1; 1 = COM2. (Note)
Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen. These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch). Index 94h 7:0 Suspend Modulation OFF Count Register (R/W) Reset Value = 00h
Suspend Signal Deasserted Count: This 8-bit value represents the number of 32 s intervals that the SUSP# pin will be deasserted to the GX-series processor. This timer, together with the Suspend Modulation ON Count Register (F0 Index 95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups.
Index 95h 7:0
Suspend Modulation ON Count Register (R/W)
Reset Value = 00h
Suspend Signal Asserted Count: This 8-bit value represents the number of 32 s intervals that the SUSP# pin will be asserted. This timer, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups.
Index 96h 7:5 4 3 2 1 Reserved: Set to 0.
Suspend Configuration Register (R/W)
Reset Value = 00h
Power Savings Mode: 0 = Enable; 1 = Disable. Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included. Suspend Mode Configuration: "Special 3 Volt Suspend" mode to support powering down a GX-series processor during Suspend. 0 = Disable; 1 = Enable. SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs. 0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA technology and power management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0).
0
Suspend Modulation Feature: 0 = Disable; 1 = Enable. When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h).
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index 97h 7 6 5 4 3 Bit 3 must be set to enable this bit. GPIO5 Edge Sense for SMI: Selects which edge transition of the GPIO5 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. GPIO4 Edge Sense for SMI: Selects which edge transition of the GPIO4 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. GPIO3 Edge Sense for SMI: Selects which edge transition of the GPIO3 pin generates an SMI. 0 = Rising; 1 = Falling. Bit 0 must be set to enable this bit. Enable GPIO7 as an External SMI Source: Allow GPIO7 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 7). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[3]. 2 Enable GPIO5 as an External SMI Source: Allow GPIO5 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 6). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[2]. 1 Enable GPIO4 as an External SMI Source: Allow GPIO4 to be an external SMI source and to generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[1]. 0 Enable GPIO3 as an External SMI Source: Allow GPIO3 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[0]. Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). Index 98h-99h 15:0 Primary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h Description GPIO Control Register 2 (R/W) Reset Value = 00h
GPIO7 Edge Sense for SMI: Selects which edge transition of the GPIO7 pin generates an SMI. 0 = Rising; 1 = Falling.
Primary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the primary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of primary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured primary hard disk's data port (configured in F0 Index 93h[5]). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[0] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0].
Index 9Ah-9Bh 15:0
Floppy Disk Idle Timer Count Register (R/W)
Reset Value = 0000h
Floppy Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the floppy disk drive is not in use so that it can be powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to any of I/O Ports 3F2h, 3F4h, 3F5h, and 3F7h (primary) or 372h, 374h, 375h, and 377h (secondary). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[1] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1].
Index 9Ch-9Dh 15:0
Parallel / Serial Idle Timer Count Register (R/W)
Reset Value = 0000h
Parallel / Serial Idle Timer Count: The idle timer loaded from this register is used to determine when the parallel and serial ports are not in use so that the ports can be power managed. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port is not considered here. The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[2] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2].
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Description Keyboard / Mouse Idle Timer Count Register (R/W) Reset Value = 0000h
Index 9Eh-9Fh 15:0
Keyboard / Mouse Idle Timer Count: The idle timer loaded from this register determines when the keyboard and mouse are not in use so that the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space when a mouse is enabled on a serial port. The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[3] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3].
Index A0h-A1h 15:0
User Defined Device 1 Idle Timer Count Register (R/W)
Reset Value = 0000h
User Defined Device 1 (UDEF1) Idle Timer Count: The idle timer loaded from this register determines when the device configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured at F0 Index C0h (base address register) and F0 Index CCh (control register). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[4] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4].
Index A2h-A3h 15:0
User Defined Device 2 Idle Timer Count Register (R/W)
Reset Value = 0000h
User Defined Device 2 (UDEF2) Idle Timer Count: The idle timer loaded from this register determines when the device configured as UDEF2 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured at F0 Index C4h (base address register) and F0 Index CDh (control register). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[5] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[5].
Index A4h-A5h 15:0
User Defined Device 3 Idle Timer Count Register (R/W)
Reset Value = 0000h
User Defined Device 3 (UDEF3) Idle Timer Count: The idle timer loaded from this register determines when the device configured as UDEF3 is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to memory or I/O address space configured at F0 Index C8h (base address register) and F0 Index CEh (control register). The timer uses a 1 second timebase. To enable this timer set F0 Index 81h[6] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[6].
Index A6h-A7h 15:0
Video Idle Timer Count Register (R/W)
Reset Value = 0000h
Video Idle Timer Count: The idle timer loaded from this register determines when the graphics subsystem has been idle as part of the Suspend determination algorithm. The 16-bit value programmed here represents the period of video inactivity after which the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the graphics controller space. The timer uses a 1 second timebase. In a GX-series processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the CS5530A via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530A also detects accesses to standard VGA space on PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used. To enable this timer set F0 Index 81h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[7].
Index A8h-A9h 15:0
Video Overflow Count Register (R/W)
Reset Value = 0000h
Video Overflow Count: Each time the Video Speedup timer (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the 100 ms timer expires before the Video Speedup timer lapses, the Video Overflow Count Register increments and the 100 ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count contained in this register may be combined with other data to determine the type of video accesses present in the system. Reserved Reset Value = xxh
Index AAh-ABh
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Description Secondary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h
Index ACh-ADh 15:0
Secondary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the secondary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of secondary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured secondary hard disk's data port (configured in F0 Index 93h[4]). The timer uses a 1 second timebase. To enable this timer set F0 Index 83h[7] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4].
Index AEh 7:0
CPU Suspend Command Register (WO)
Reset Value = 00h
Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] = 0) and all SMI status bits are 0, a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt condition. If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked, allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin. Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wakeup the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events.
Index AFh 7:0
Suspend Notebook Command Register (WO)
Reset Value = 00h
Software CPU Stop Clock Suspend (Write Only): A write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state. Following this handshake, the SUSP_3V pin is asserted. The SUSP_3V pin is intended to be used to stop all system clocks. Upon a Resume event (see Note), the SUSP_3V pin is deasserted. After a slight delay, the CS5530A deasserts the SUSP# signal. Once the clocks are stable, the processor deasserts SUSPA# and system operation resumes. Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wakeup the system from Suspend when the clocks are stopped.
Index B0h-B3h Index B4h 7:0
Reserved Floppy Port 3F2h Shadow Register (RO)
Reset Value = xxh Reset Value = xxh
Floppy Port 3F2h Shadow (Read Only): Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
Index B5h 7:0
Floppy Port 3F7h Shadow Register (RO)
Reset Value = xxh
Floppy Port 3F7h Shadow (Read Only): Last written value of I/O Port 3F7h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
Index B6h 7:0
Floppy Port 1F2h Shadow Register (RO)
Reset Value = xxh
Floppy Port 1F2h Shadow (Read Only): Last written value of I/O Port 1F2h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
Index B7h 7:0
Floppy Port 1F7h Shadow Register (RO)
Reset Value = xxh
Floppy Port 1F7h Shadow (Read Only): Last written value of I/O Port 1F7h. Required for support of FDC power ON/OFF and Save-to-Disk/RAM coherency. This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when the register is being read. It is provided here to assist in a Save-to-Disk operation.
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index B8h 7:0 Description DMA Shadow Register (RO) Reset Value = xxh
DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. DMA Channel 0 Mode Register DMA Channel 1 Mode Register DMA Channel 2 Mode Register DMA Channel 3 Mode Register DMA Channel 4 Mode Register DMA Channel 5 Mode Register DMA Channel 6 Mode Register DMA Channel 7 Mode Register DMA Channel Mask Register (bit 0 is channel 0 mask, etc.) DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 ms, all other bits are 0) PIC Shadow Register (RO) Reset Value = xxh
Index B9h 7:0
PIC Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interrupt Controller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. PIC1 ICW1 PIC1 ICW2 PIC1 ICW3 PIC1 ICW4 - Bits [7:5] of ICW4 are always 0 PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1 PIC2 ICW1 PIC2 ICW2 PIC2 ICW3 PIC2 ICW4 - Bits [7:5] of ICW4 are always 0 PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note) PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1
Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register value, then with the shadow register value ORed with C0h. Index BAh 7:0 PIT Shadow Register (RO) Reset Value = xxh
PIT Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interval Timer registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. Counter 0 LSB (least significant byte) 2. Counter 0 MSB 3. Counter 1 LSB 4. Counter 1 MSB 5. Counter 2 LSB 6. Counter 2 MSB 7. Counter 0 Command Word 8. Counter 1 Command Word 9. Counter 2 Command Word Note: The LSB/MSB of the count is the Counter base value, not the current value. Bits [7:6] of the command words are not used.
Index BBh 7:0
RTC Index Shadow Register (RO)
Reset Value = xxh
RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index register (I/O Port 070h).
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index BCh 7:4 Description Clock Stop Control Register (R/W) Reset Value = 00h
PLL Delay: The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before starting execution. This delay is only invoked if the STP_CLK bit (bit 0) was set. The four-bit field allows values from 0 to 15 ms. 0000 = 0 ms 0001 = 1 ms 0010 = 2 ms 0011 = 3 ms 0100 = 4 ms 0101 = 5 ms 0110 = 6 ms 0111 = 7 ms 1000 = 8 ms 1001 = 9 ms 1010 = 10 ms 1011 = 11 ms 1100 = 12 ms 1101 = 13 ms 1110 = 14 ms 1111 = 15 ms
3:1 0
Reserved: Set to 0. CPU Clock Stop: 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.
Note: This register configures the CS5530A to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system. A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as: 0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped. When a break/resume event occurs, it releases the CPU halt condition. 1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU and system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay programmed in bits [7:4] will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin. Index BDh-BFh Index C0h-C3h 31:0 Reserved User Defined Device 1 Base Address Register (R/W) Reset Value = xxh Reset Value = 00000000h
User Defined Device 1 (UDEF1) Base Address [31:0]: This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh). User Defined Device 2 Base Address Register (R/W) Reset Value = 00000000h
Index C4h-C7h 31:0
User Defined Device 2 (UDEF2) Base Address [31:0]: This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh). User Defined Device 3 Base Address Register (R/W) Reset Value = 00000000h
Index C8h-CBh 31:0
User Defined Device 3 (UDEF3) Base Address [31:0]: This 32-bit register supports power management (trap and idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh). User Defined Device 1 Control Register (R/W) Memory or I/O Mapped: User Defined Device 1 is: 0 = I/O; 1 = Memory. Mask If bit 7 = 0 (I/O): Bit 6 Bit 5 Bits 4:0 If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. 0 = Disable write cycle tracking 1 = Enable write cycle tracking 0 = Disable read cycle tracking 1 = Enable read cycle tracking Mask for address bits A[4:0] Reset Value = 00h
Index CCh 7 6:0
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index CDh 7 6:0 Description User Defined Device 2 Control Register (R/W) Memory or I/O Mapped: User Defined Device 2 is: 0 = I/O; 1 = Memory. Mask If bit 7 = 0 (I/O): Bit 6 Bit 5 Bits 4:0 If bit 7 = 1 (M/IO): Bits 6:0 Index CEh 7 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. User Defined Device 3 Control Register (R/W) Memory or I/O Mapped: User Defined Device 3 is: 0 = I/O; 1 = Memory. Mask If bit 7 = 0 (I/O): Bit 6 Bit 5 Bits 4:0 If bit 7 = 1 (M/IO): Bits 6:0 Index CFh Index D0h 7:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Reserved Software SMI Register (WO) Reset Value = xxh Reset Value = 00h Note: A "1" in a mask bit means that the address bit is ignored for comparison. 0 = Disable write cycle tracking 1 = Enable write cycle tracking 0 = Disable read cycle tracking 1 = Enable read cycle tracking Mask for address bits A[4:0] Reset Value = 00h Note: A "1" in a mask bit means that the address bit is ignored for comparison. 0 = Disable write cycle tracking 1 = Enable write cycle tracking 0 = Disable read cycle tracking 1 = Enable read cycle tracking Mask for address bits A[4:0] Reset Value = 00h
Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions. Reserved Timer Test Register (R/W) Reset Value = xxh Reset Value = 00h
Index D1h-EBh Index ECh 7:0
Timer Test Value: The Timer Test Register is intended only for test and debug purposes. It is not intended for setting operational timebases. Reserved Reset Value = xxh
Index EDh-F3h
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index F4h 7:5 4 Reserved Game Port SMI Status (Read to Clear): SMI was caused by a R/W access to game port (I/O Port 200h and 201h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. Game Port Read SMI generation enabling is at F0 Index 83h[4]. Game Port Write SMI generation enabling is at F0 Index 53h[3]. 3 GPIO7 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO7 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[3]. 2 GPIO5 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO5 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[2]. 1 GPIO4 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO4 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[1]. 0 GPIO3 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO3 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 97h[0]. Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on various power-management SMI events. Reading this register clears the SMI status bits. A readonly (mirror) version of this register exists at F0 Index 84h. Description Second Level Power Management Status Register 1 (RC) Reset Value = 00h
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index F5h 7 Description Second Level Power Management Status Register 2 (RC) Reset Value = 00h
Video Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Video Idle Timer Count Register (F0 Index A6h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[7].
6
User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[6].
5
User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF2 Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[5].
4
User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF1 Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[4].
3
Keyboard/Mouse Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[3].
2
Parallel/Serial Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[2].
1
Floppy Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Floppy Disk Idle Timer Count Register (F0 Index 9Ah)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[1].
0
Primary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Primary Hard Disk Idle Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 81h[0].
Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the duration configured in the Idle Timer Count register for that device, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 85h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead.
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Register Descriptions (Continued)
Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index F6h 7 Description Second Level Power Management Status Register 3 (RC) Reset Value = 00h
Video Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the Video I/O Trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[7].
6 5
Reserved (Read Only) Secondary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the secondary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[6].
4
Secondary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Hard Disk Idle Timer Count Register (F0 Index ACh)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 83h[7].
3
Keyboard/Mouse Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the keyboard or mouse? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[3].
2
Parallel/Serial Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to either the serial or parallel ports? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[2].
1
Floppy Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the floppy disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[1].
0
Primary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the primary hard disk? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 82h[0].
Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the device while the trap was enabled, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F0 Index 86h may be read instead.
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Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit Index F7h 7 Description Second Level Power Management Status Register 4 (RO/RC) Reset Value = 00h
GPIO2 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO2 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[2].
6
GPIO1 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO1 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[1].
5
GPIO0 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO0 pin? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 92h[0].
4 3
Lid Position (Read Only): This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid switch indicator, this bit reflects the state of the pin. Lid Switch SMI Status (Read to Clear): SMI was caused by a transition on the GPIO6 (lid switch) pin? 0 = No; 1 = Yes. For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index 92h[6] =1).
2
Codec SDATA_IN SMI Status (Read to Clear): SMI was caused by an AC97 codec producing a positive edge on SDATA_IN? 0 = No; 1 = Yes. This is the second level of status is reporting. The top level status is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling is at F0 Index 80h[5].
1
RTC Alarm (IRQ8) SMI Status (Read to Clear): SMI was caused by an RTC interrupt? 0 = No; 1 = Yes. This SMI event can only occur while in 3V Suspend and RTC interrupt occurs. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
0
ACPI Timer SMI Status (Read to Clear): SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation configuration is at F0 Index 83h[5].
Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI. This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 87h. Index F8h-FFh Reserved Reset Value = xxh
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4.3.2 SMI Status and ACPI Timer Registers - Function 1 The register space for the SMI status and ACPI Timer registers is divided into two sections. The first section is used to configure the PCI portion of this support hardware. A Base Address Register at F1 Index 10h (F1BAR) points to the base address of where the second portion of the register space is located. This second section contains the SMI status and ACPI timer support registers. Note: The ACPI Timer Count Register is accessible through F1BAR+Memory Offset 1Ch and I/O Port 121Ch. Table 4-16 shows the PCI header registers of F1. The memory mapped registers accessed through F1BAR are shown in Table 4-17. If the Power Management Configuration Trap bit (F0 Index 41h[3]) is enabled, an access to the PCI header registers causes an SMI. Access through F1BAR is not affected by this bit.
Table 4-16. F1 Index xxh: PCI Header Registers for SMI Status and ACPI Timer
Bit Description Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) Reset Value = 1078h Reset Value = 0101h Reset Value = 0000h
Index 00h-01h Index 02h-03h Index 04h-05h 15:2 1 0 Reserved (Read Only)
Memory Space: Allow CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable. This bit must be enabled to access memory offsets through F1BAR (F1 Index 10h). Reserved (Read Only) PCI Status Register (RO) Device Revision ID Register (RO) PCI Class Code Register (RO) PCI Cache Line Size Register (RO) PCI Latency Timer Register (RO) PCI Header Type (RO) PCI BIST Register (RO) Base Address Register -- F1BAR (R/W) Reset Value = 0280h Reset Value = 00h Reset Value = 068000h Reset Value = 00h Reset Value = 00h Reset Value = 00h Reset Value = 00h Reset Value = 00000000h
Index 06h-07h Index 08h Index 09h-0Bh Index 0Ch Index 0Dh Index 0Eh Index 0Fh Index 10h-13h
This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h), indicating a 256-byte memory address range. Refer to Table 4-17 for the SMI status and ACPI timer registers bit formats and reset values. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped. Note: The ACPI Timer Count Register is accessible through F1BAR+Memory Offset 1Ch and I/O Port 121Ch. 31:8 7:0 SMI Status/Power Management Base Address Address Range (Read Only) Reserved Reserved Reset Value = 00h Reset Value = xxh
Index 14h-3Fh Index 40h-FFh
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Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers
Bit Description Top Level SMI Status Mirror Register (RO) Reset Value = 0000h
Offset 00h-01h 15
Suspend Modulation Enable Mirror (Read Only): This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h) must be cleared on exit. SMI Source is USB (Read Only): SMI was caused by USB activity? 0 = No; 1 = Yes. SMI generation is configured in F0 Index 42h[7:6]. SMI Source is Warm Reset Command (Read Only): SMI was caused by Warm Reset command? 0 = No; 1 = Yes. SMI Source is NMI (Read Only): SMI was caused by NMI activity? 0 = No; 1 = Yes. Reserved (Read Only): Always reads 0. SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read Only): SMI was caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register Space? 0 = No; 1 = Yes. The next level of status is found at F1BAR+Memory Offset 04h/06h. SMI Source is Software Generated (Read Only): SMI was caused by software? 0 = No; 1 = Yes. SMI on an A20M# Toggle (Read Only): SMI was caused by an access to either Port 092h or the keyboard command which initiates an A20M# SMI? 0 = No; 1 = Yes. This method of controlling the internal A20M# in the GX-series processor is used instead of a pin. SMI generation enabling is at F0 Index 53h[0].
14 13 12 11:10 9
8 7
6
SMI Source is a VGA Timer Event (Read Only): SMI was caused by the expiration of the VGA Timer (F0 Index 8Eh)? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[3]. SMI Source is Video Retrace (IRQ2) (Read Only): SMI was caused by a video retrace event as decoded from the serial connection (PSERIAL register, bit 7) from the GX-series processor? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[2]. Reserved (Read Only): Always reads 0. SMI Source is Audio Interface (Read Only): SMI was caused by the audio interface? 0 = No; 1 = Yes. The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h. SMI Source is Power Management Event (Read Only): SMI was caused by one of the power management resources? 0 = No; 1 = Yes. The next level of status is found at F0 Index 84h-87h/F4h-F7h. Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9.
5
4:2 1 0
Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 02h.
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Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued)
Bit Description Top Level SMI Status Register (RC) Reset Value = 0000h
Offset 02h-03h 15
Suspend Modulation Enable Mirror (Read to Clear): This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h) must be cleared on exit. SMI Source is USB (Read to Clear): SMI was caused by USB activity? 0 = No; 1 = Yes. SMI generation is configured in F0 Index 42h[7:6]. SMI Source is Warm Reset Command (Read to Clear): SMI was caused by Warm Reset command? 0 = No; 1 = Yes. SMI Source is NMI (Read to Clear): SMI was caused by NMI activity? 0 = No; 1 = Yes. Reserved (Read to Clear): Always reads 0. SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read to Clear): SMI was caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register Space? 0 = No; 1 = Yes. The next level of status is found at F1BAR+Memory Offset 04h/06h. SMI Source is Software Generated (Read to Clear): SMI was caused by software? 0 = No; 1 = Yes. SMI on an A20M# Toggle (Read to Clear): SMI was caused by an access to either Port 092h or the keyboard command which initiates an A20M# SMI? 0 = No; 1 = Yes. This method of controlling the internal A20M# in the GX-series processor is used instead of a pin. SMI generation enabling is at F0 Index 53h[0].
14 13 12 11:10 9
8 7
6
SMI Source is a VGA Timer Event (Read to Clear): SMI was caused by the expiration of the VGA Timer (F0 Index 8Eh)? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[3]. SMI Source is Video Retrace (IRQ2) (Read to Clear): SMI was caused by a video retrace event as decoded from the serial connection (PSERIAL register, bit 7) from the GX-series processor? 0 = No; 1 = Yes. SMI generation enabling is at F0 Index 83h[2]. Reserved (Read to Clear): Always reads 0. SMI Source is Audio Interface (Read to Clear): SMI was caused by the audio interface? 0 = No; 1 = Yes. The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h. SMI Source is Power Management Event (Read to Clear): SMI was caused by one of the power management resources? 0 = No; 1 = Yes. The next level of status is found at F0 Index 84h-87h/F4h-F7h. Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9.
5
4:2 1 0
Note: Reading this register clears all the SMI status bits. Note that bits 9, 1, and 0 have another level (second) of status reporting. A read-only "Mirror" version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.
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Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued)
Bit Description Second Level General Traps & Timers SMI Status Mirror Register (RO) Reset Value = 0000h
Offset 04h-05h 15:6 5
Reserved (Read Only) PCI Function Trap (Read Only): SMI was caused by a trapped configuration cycle (listed below)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. Trapped access to F0 PCI header registers other than F0 Index 40h-43h; SMI generation enabling is at F0 Index 41h[0]. Trapped access to F1 PCI header registers; SMI generation enabling is at F0 Index 41h[3]. Trapped access to F2 PCI header registers; SMI generation enabling is at F0 Index 41h[6]. Trapped access to F3 PCI header registers; SMI generation enabling is at F0 Index 42h[0]. Trapped access to F4 PCI header registers; SMI generation enabling is at F0 Index 42h[1].
4
SMI Source is Trapped Access to User Defined Device 3 (Read Only): SMI was caused by a trapped I/O or memory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[6].
3
SMI Source is Trapped Access to User Defined Device 2 (Read Only): SMI was caused by a trapped I/O or memory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[5].
2
SMI Source is Trapped Access to User Defined Device 1 (Read Only): SMI was caused by a trapped I/O or memory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[4].
1
SMI Source is Expired General Purpose Timer 2 (Read Only): SMI was caused by the expiration of General Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[1].
0
SMI Source is Expired General Purpose Timer 1 (Read Only): SMI was caused by the expiration of General Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[0].
Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 06h.
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Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued)
Bit Description Second Level General Traps & Timers SMI Status Register (RC) Reset Value = 0000h
Offset 06h-07h 15:6 5
Reserved (Read to Clear) PCI Function Trap (Read to Clear): SMI was caused by a trapped configuration cycle (listed below)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. Trapped access to F0 PCI header registers other than Index 40h-43h; SMI generation enabling is at F0 Index 41h[0]. Trapped access to F1 PCI header registers; SMI generation enabling is at F0 Index 41h[3]. Trapped access to F2 PCI header registers; SMI generation enabling is at F0 Index 41h[6]. Trapped access to F3 PCI header registers; SMI generation enabling is at F0 Index 42h[0]. Trapped access to F4 PCI header registers; SMI generation enabling is at F0 Index 42h[1].
4
SMI Source is Trapped Access to User Defined Device 3 (Read to Clear): SMI was caused by a trapped I/O or memory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[6].
3
SMI Source is Trapped Access to User Defined Device 2 (Read to Clear): SMI was caused by a trapped I/O or memory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[5].
2
SMI Source is Trapped Access to User Defined Device 1 (Read to Clear): SMI was caused by a trapped I/O or memory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 82h[4].
1
SMI Source is Expired General Purpose Timer 2 (Read to Clear): SMI was caused by the expiration of General Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[1].
0
SMI Source is Expired General Purpose Timer 1 (Read to Clear): SMI was caused by the expiration of General Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9]. SMI generation enabling is at F0 Index 83h[0].
Note: Reading this register clears all the SMI status bits. A read-only "Mirror" version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead. Offset 08h-09h 15:0 SMI Speedup Disable Register (Read to Enable) Reset Value = 0000h
SMI Speedup Disable: If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register invokes the SMI handler to re-enable Suspend Modulation. The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has no effect.
Offset 0Ah-1Bh
Reserved
Reset Value = xxh
Offset 1Ch-1Fh (Note)
ACPI Timer Count Register (RO)
Reset Value = 00FFFFFCh
ACPI_COUNT (Read Only): This read-only register provides the current value of the ACPI timer. The timer counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. 31:24 23:0 Reserved: Always returns 0. Counter
Note: The ACPI Timer Count Register is also accessible through I/O Port 121Ch.
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Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued)
Bit Description Reserved Reset Value = xxh
Offset 20h-4Fh Offset 50h-FFh
The memory mapped registers located here (F1BAR+Memory Offset 50h-FFh) can also be accessed at F0 Index 50h-FFh. The preferred method is to program these register through the F0 register space. Refer to Table 4-15 "F0 Index xxh: PCI Header and Bridge Configuration Registers" on page 153 for bit information regarding these registers.
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4.3.3 IDE Controller Registers - Function 2 The register space for the IDE controllers is divided into two sections. The first section is used to configure the PCI portion of the controller. A Base Address Register at F2 Index 20h points to the base address of where the second portion of the register space is located. This second section contains the registers used by the IDE controllers to carry out operations. Table 4-18 shows the PCI header registers of F2. The I/O mapped registers, accessed through F2BAR, are shown in Table 4-19. If the IDE Configuration Trap bit (F0 Index 41h[6]) is set, access to the PCI header registers causes an SMI. Access through F2BAR is not affected by this bit.
Table 4-18. F2 Index xxh: PCI Header Registers for IDE Configuration
Bit Description Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) Reset Value = 1078h Reset Value = 0102h Reset Value = 0000h
Index 00h-01h Index 02h-03h Index 04h-05h 15:3 2 1 0 Reserved (Read Only) Reserved Reserved (Read Only)
I/O Space: Allow CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable. This bit must be enabled to access I/O offsets through F2BAR (F2 Index 20h). PCI Status Register (RO) Device Revision ID Register (RO) PCI Class Code Register (RO) PCI Cache Line Size Register (RO) PCI Latency Timer Register (RO) PCI Header Type (RO) PCI BIST Register (RO) Reserved Base Address Register - F2BAR (R/W) Reset Value = 0280h Reset Value = 00h Reset Value = 010180h Reset Value = 00h Reset Value = 00h Reset Value = 00h Reset Value = 00h ReservedReset Value = 00h Reset Value = 00000001h
Index 06h-07h Index 08h Index 09h-0Bh Index 0Ch Index 0Dh Index 0Eh Index 0Fh Index 10h-1Fh Index 20h-23h
This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [6:0] are read only (0000 001), indicating a 128-byte I/O address range. Refer to Table 4-19 for the IDE configuration registers bit formats and reset values. 31:7 6:0 Bus Mastering IDE Base Address Address Range (Read Only) Reserved Reserved Reset Value = 00h Reset Value = xxh
Index 24h-3Fh Index 40h-FFh
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Table 4-19. F2BAR+I/O Offset xxh: IDE Configuration Registers
Bit Offset 00h 7:4 3 2:1 0 Description IDE Bus Master 0 Command Register -- Primary (R/W) Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Sets the direction of bus master transfers. 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the bus master. 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 to 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is discarded. This bit should be reset after completion of data transfer. Offset 01h Offset 02h 7 6 5 4:3 2 1 0 Offset 03h Offset 04h-07h 31:2 Reserved IDE Bus Master 0 Status Register -- Primary (R/W) Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes; 1 = No (simplex mode). Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Reserved: Set to 0. Must return 0 on reads. Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes. Reserved IDE Bus Master 0 PRD Table Address -- Primary (R/W) Reset Value = xxh Reset Value = 00000000h Reset Value = xxh Reset Value = 00h Reset Value = 00h
Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 0. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD.
1:0 Offset 08h 7:4 3 2:1 0
Reserved: Set to 0. IDE Bus Master 1 Command Register -- Secondary (R/W) Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Sets the direction of bus master transfers. 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the bus master. 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 = 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is discarded. This bit should be reset after completion of data transfer. Reset Value = 00h
Offset 09h Offset 0Ah 7 6 5 4:3 2 1 0
Reserved IDE Bus Master 1 Status Register -- Secondary (R/W) Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes; 1 = No (simplex mode). Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers. 0 = Disable; 1 = Enable. Reserved: Set to 0. Must return 0 on reads. Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes. Write 1 to clear. Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes.
Reset Value = xxh Reset Value = 00h
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Table 4-19. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued)
Bit Offset 0Bh Offset 0Ch-0Fh 31:2 Description Reserved IDE Bus Master 1 PRD Table Address -- Secondary (R/W) Reset Value = xxh Reset Value = 00000000h
Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 1. When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD.
1:0
Reserved: Set to 0. Reserved Channel 0 Drive 0 PIO Register (R/W) Reset Value = xxh Reset Value = 0000E132h (Note)
Offset 10h-1Fh Offset 20h-23h
If Offset 24h[31] = 0, Format 0: Selects slowest PIOMODE per channel for commands. Format 0 settings for: PIO Mode 0 = 00009172h PIO Mode 1 = 00012171h PIO Mode 2 = 00020080h PIO Mode 3 = 00032010h PIO Mode 4 = 00040010h 31:20 19:16 15:12 11:8 7:4 3:0 Reserved: Set to 0. PIOMODE: PIO mode t2I: Recovery time (value + 1 cycle) t3: IDE_IOW# data setup time (value + 1 cycle) t2W: IDE_IOW# width minus t3 (value + 1 cycle) t1: Address Setup Time (value + 1 cycle)
If Offset 24h[31] = 1, Format 1: Allows independent control of command and data. Format 1 settings for: PIO Mode 0 = 9172D132h PIO Mode 1 = 21717121h PIO Mode 2 = 00803020h PIO Mode 3 = 20102010h PIO Mode 4 = 00100010h 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 t2IC: Command cycle recovery time (value + 1 cycle) t3C: Command cycle IDE_IOW# data setup (value + 1 cycle) t2WC: Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) t1C: Command cycle address setup time (value + 1 cycle) t2ID: Data cycle recovery time (value + 1 cycle) t3D: Data cycle IDE_IOW# data setup (value + 1 cycle) t2WD: Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle) t1D: Data cycle address Setup Time (value + 1 cycle)
Note: The reset value of this register is not a valid PIO Mode.
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Table 4-19. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued)
Bit Description Channel 0 Drive 0 DMA Control Register (R/W) Reset Value = 00077771h
Offset 24h-27h If bit 20 = 0, Multiword DMA
Settings for: Multiword DMA Mode 0 = 00077771h Multiword DMA Mode 1 = 00012121h Multiword DMA Mode 2 = 00002020h 31 30:21 20 19:16 15:12 11:8 7:4 3:0 PIO Mode Format: 0 = Format 0; 1 = Format 1. Reserved: Set to 0. DMA Operation: 0 = Multiword DMA; 1 = Ultra DMA. tKR: IDE_IOR# recovery time (4-bit) (value + 1 cycle) tDR: IDE_IOR# pulse width (value + 1 cycle) tKW: IDE_IOW# recovery time (4-bit) (value + 1 cycle) tDW: IDE_IOW# pulse width (value + 1 cycle) tM: IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1#
If bit 20 = 1, Ultra DMA Settings for: Ultra DMA Mode 0 = 00921250h Ultra DMA Mode 1 = 00911140h Ultra DMA Mode 2 = 00911030h 31 30:21 20 19:16 15:12 11:8 7:4 3:0 PIO Mode Format: 0 = Format 0; 1 = Format 1. Reserved: Set to 0. DMA Operation: 0 = Multiword DMA, 1 = Ultra DMA. tCRC: CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS) tSS: UDMA out (value + 1 cycle) tCYC: Data setup and cycle time UDMA out (value + 2 cycles) tRP: Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock. tACK: IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle) Channel 0 Drive 1 PIO Register (R/W) Reset Value = 0000E132h
Offset 28h-2Bh
Channel 0 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 2Ch-2Fh Channel 0 Drive 1 DMA Control Register (R/W) Reset Value = 00077771h
Channel 0 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 30h-33h Channel 1 Drive 0 PIO Register (R/W) Reset Value = 0000E132h
Channel 1 Drive 0 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 34h-37h Channel 1 Drive 0 DMA Control Register (R/W) Reset Value = 00077771h
Channel 1 Drive 0 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 38h-3Bh Channel 1 Drive 1 PIO Register (R/W) Reset Value = 0000E132h
Channel 1 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions. Offset 3Ch-3Fh Channel 1 Drive 1 DMA Control Register (R/W) Reset Value = 00077771h
Channel 1 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 40h-FFh Reserved Reset Value = xxh
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Register Descriptions (Continued)
4.3.4 XpressAUDIO Registers - Function 3 The register space for XpressAUDIO is divided into two sections. The first section is used to configure the PCI portion of the audio interface hardware. A Base Address Register at F3 Index 10h (F3BAR) points to the base address of where the second portion of the register space is located. This second section contains the control and data registers of the audio interface. Table 4-20 shows the PCI header registers of F3. The memory mapped registers accessed through F3BAR are shown in Table 4-21. If the F3 Audio Configuration Trap bit (F0 Index 42h[0]) is enabled, an access to the PCI header registers causes an SMI. Access through F3BAR is not affected by this bit.
Table 4-20. F3 Index xxh: PCI Header Registers for XpressAUDIO
Bit Description Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) Reset Value = 1078h Reset Value = 0103h Reset Value = 0000h
Index 00h-01h Index 02h-03h Index 04h-05h 15:3 2 1 0 Reserved (Read Only) Reserved (Read/Write)
Memory Space: Allow CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable. This bit must be enabled to access memory offsets through F3BAR (F3 Index 10h). Reserved (Read Only) PCI Status Register (RO) Device Revision ID Register (RO) PCI Class Code Register (RO) PCI Cache Line Size Register (RO) PCI Latency Timer Register (RO) PCI Header Type (RO) PCI BIST Register (RO) Base Address Register - F3BAR (R/W) Reset Value = 0280h Reset Value = 00h Reset Value = 040100h Reset Value = 00h Reset Value = 00h Reset Value =00h Reset Value = 00h Reset Value = 00000000h
Index 06h-07h Index 08h Index 09h-0Bh Index 0Ch Index 0Dh Index 0Eh Index 0Fh Index 10h-13h
This register sets the base address of the memory mapped audio interface control register block. This is a 128-byte block of registers used to control the audio FIFO and codec interface, as well as to support SMIs produced by VSA technology. Bits [6:0] are read only (0000000), indicating a 128-byte memory address range. Refer to Table 4-21 for the bit formats and reset values of the XpressAUDIO registers. 31:7 6:0 Audio Interface Base Address Address Range (Read Only) Reserved Reserved Reset Value = 00h Reset Value = xxh
Index 14h-3Fh Index 40h-FFh
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers
Bit Description Codec GPIO Status Register (R/W) Reset Value = 00100000h
Offset 00h-03h 31 30
Codec GPIO Interface: 0 = Disable; 1 = Enable. Codec GPIO SMI: Allow codec GPIO interrupt to generate an SMI. 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1].
29:21 20 19:0
Reserved: Set to 0. Codec GPIO Status Valid (Read Only): Is the status read valid? 0 = Yes; 1 = No. Codec GPIO Pin Status (Read Only): This is the GPIO pin status that is received from the codec in slot 12 on SDATA_IN signal. Codec GPIO Control Register (R/W) Reset Value = 00000000h
Offset 04h-07h 31:20 19:0 Reserved: Set to 0.
Codec GPIO Pin Data: This is the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal. Codec Status Register (R/W) Reset Value = 00000000h
Offset 08h-0Bh 31:24 23
Codec Status Address (Read Only): Address of the register for which status is being returned. This address comes from slot 1 bits [19:12]. Codec Serial INT SMI: Allow codec serial interrupt to generate an SMI. 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1].
22 21 20 19 18 17 16 15:0
SYNC Pin: Selects SYNC pin level. 0 = Low; 1 = High. Enable SDATA_IN2: Pin AE24 function selection. 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). Audio Bus Master 5 AC97 Slot Select: Selects slot for Audio Bus Master 5 to receive data. 0 = Slot 6; 1 = Slot 11. Audio Bus Master 4 AC97 Slot Select: Selects slot for Audio Bus Master 4 to transmit data. 0 = Slot 6; 1 = Slot 11. Reserved: Set to 0. Status Tag (Read Only): Determines if the status in bits [15:0] is new or not. 0 = Not new; 1 = New. Codec Status Valid (Read Only): Is the status in bits [15:0] valid? 0 = No; 1 = Yes. Codec Status (Read Only): This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits [19:4] are used from slot 2. Codec Command Register (R/W) Reset Value = 00000000h
Offset 0Ch-0Fh 31:24 23:22
Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. CS5530A Codec Communication: Selects which codec to communicate with. 00 = Primary codec 10 = Third codec 01 = Secondary codec 11 = Fourth codec Note: 00 and 01 are the only valid settings for these bits. Reserved: Set to 0. Codec Command Valid: Is the command in bits [15:0] valid? 0 = No; 1 = Yes. This bit is set by hardware when a command is loaded. It remains set until the command has been sent to the codec. Codec Command: This is the command being sent to the codec in bits [19:12] of slot 2 on SDATA_OUT.
21:17 16 15:0
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Description Second Level Audio SMI Status Register (RC) Reset Value = 0000h
Offset 10h-11h 15:8 7 Reserved: Set to 0.
Audio Bus Master 5 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 5? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1).
6
Audio Bus Master 4 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 4? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1).
5
Audio Bus Master 3 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 3? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1).
4
Audio Bus Master 2 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 2? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1).
3
Audio Bus Master 1 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 1? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1).
2
Audio Bus Master 0 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 0? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1).
1
Codec Serial or GPIO Interrupt SMI Status (Read to Clear): SMI was caused by a serial or GPIO interrupt from codec? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1.
0
I/O Trap SMI Status (Read to Clear): SMI was caused by an I/O trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1].
Note: Reading this register clears the status bits. Note that bit 0 has another level (third) of SMI status reporting. A read-only "Mirror" version of this register exists at F3BAR+Memory Offset 12h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Description Second Level Audio SMI Status Mirror Register (RO) Reset Value = 0000h
Offset 12h-13h 15:8 7 Reserved: Set to 0.
Audio Bus Master 5 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 5? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1).
6
Audio Bus Master 4 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 4? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1).
5
Audio Bus Master 3 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 3? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1).
4
Audio Bus Master 2 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 2? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1).
3
Audio Bus Master 1 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 1? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1).
2
Audio Bus Master 0 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 0? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1).
1
Codec Serial or GPIO Interrupt SMI Status (Read Only): SMI was caused by a serial or GPIO interrupt from codec? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1.
0
I/O Trap SMI Status (Read Only): SMI was caused by an I/O trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1].
Note: Reading this register does not clear the status bits. See F3BAR+Memory Offset 10h.
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Description I/O Trap SMI and Fast Write Status Register (RO/RC) Reset Value = 00000000h
Offset 14h-17h 31:24 23:16 15 14 13
Fast Path Write Even Access Data (Read Only): These bits contain the data from the last Fast Path Write Even access. These bits change only on a fast write to an even address. Fast Path Write Odd Access Data (Read Only): These bits contain the data from the last Fast Path Write Odd access. These bits change on a fast write to an odd address, and also on any non-fast write. Fast Write A1 (Read Only): This bit contains the A1 value for the last Fast Write access. Read or Write I/O Access (Read Only): Last trapped I/O access was a read or a write? 0 = Read; 1 = Write. Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM I/O Trap? 0 = No; 1 = Yes. (Note) Fast Path Write must be enabled, F3BAR+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is disabled, the SMI is reported in bit 10 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2].
12
DMA Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the DMA I/O Trap? 0 = No; 1 = Yes. (Note) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[8:7].
11
MPU Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the MPU I/O Trap? 0 = No; 1 = Yes. (Note) This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[6:5].
10
Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM I/O Trap? 0 = No; 1 = Yes. (Note) Fast Path Write must be disabled, F3BAR+Memory Offset 18h[11] = 0, for the SMI to be reported here. If Fast Path Write is enabled, the SMI is reported in bit 13 of this register. This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[2].
9:0
X-Bus Address (Read Only): Bits [9:0] contain the captured ten bits of X-Bus address.
Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of the DMA, MPU, or sound card status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set to a 1.
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Description I/O Trap SMI Enable Register (R/W) Reset Value = 0000h
Offset 18h-19h 15:12 11 Reserved: Set to 0.
Fast Path Write Enable: Fast Path Write (an SMI is not generated on certain writes to specified addresses). 0 = Disable; 1 = Enable. In Fast Path Write, the CS5530A responds to writes to the following addresses: 388h, 38Ah and 38Bh; 2x0h, 2x2h, and 2x8h.
10:9 8
Fast Read: These two bits hold part of the response that the CS5530A returns for reads to several I/O locations. High DMA I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port C0h-DFh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12].
7
Low DMA I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 00h-0Fh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12].
6
High MPU I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 330h and 331h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11].
5
Low MPU I/O Trap: I0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 300h and 301h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11].
4
Fast Path Read Enable/SMI Disable: Read Fast Path (an SMI is not generated on reads from specified addresses). 0 = Disable; 1 = Enable. In Fast Path Read the CS5530A responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1h, 2x2h, 2x3h, 2x8h and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible.
3
FM I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 388h to 38Bh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0].
2
Sound Card I/O Trap: 0 = Disable; 1 = Enable If this bit is enabled and an access occurs in the address ranges selected by bits [1:0], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[10].
1:0
Sound Card Address Range Select: These bits select the address range for the sound card I/O trap. 00 = I/O Port 220h-22Fh 01 = I/O Port 240h-24Fh 10 = I/O Port 260h-26Fh 11 = I/O Port 280h-28Fh
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Description Internal IRQ Enable Register (R/W) Reset Value = 0000h
Offset 1Ah-1Bh 15 14 13 12 11 10 9 8 7 6 5 4 3 2:0
IRQ15 Internal: Configure IRQ15 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ14 Internal: Configure IRQ14 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0. IRQ12 Internal: Configure IRQ12 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ11 Internal: Configure IRQ11 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ10 Internal: Configure IRQ10 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ9 Internal: Configure IRQ9 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0. IRQ7 Internal: Configure IRQ7 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0. IRQ5 Internal: Configure IRQ5 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ4 Internal: Configure IRQ4 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. IRQ3 Internal: Configure IRQ3 for internal (software) or external (hardware) use. 0 = External; 1 = Internal. Reserved: Set to 0.
Note: Must be read and written as a WORD. Offset 1Ch-1Dh 15 14 13 12 11 10 9 8 7 6 5 4 3 2:0 Internal IRQ Control Register (R/W) Reset Value = 0000h
Assert Masked Internal IRQ15: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ14: 0 = Disable; 1 = Enable. Reserved: Set to 0. Assert Masked Internal IRQ12: 0 = Disable; 1 = Enable. Assert masked internal IRQ11: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ10: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ9: 0 = Disable; 1 = Enable. Reserved: Set to 0. Assert Masked Internal IRQ7: 0 = Disable; 1 = Enable. Reserved: Set to 0. Assert Masked Internal IRQ5: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ4: 0 = Disable; 1 = Enable. Assert Masked Internal IRQ3: 0 = Disable; 1 = Enable. Reserved: Set to 0. Internal IRQ Mask Register (Write Only) Reset Value = xxxxh
Offset 1Eh-1Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2:0
Mask Internal IRQ15: 0 = Disable; 1 = Enable. Mask Internal IRQ14: 0 = Disable; 1 = Enable. Reserved: Set to 0. Mask Internal IRQ12: 0 = Disable; 1 = Enable. Mask Internal IRQ11: 0 = Disable; 1 = Enable. Mask Internal IRQ10: 0 = Disable; 1 = Enable. Mask Internal IRQ9: 0 = Disable; 1 = Enable. Reserved: Set to 0. Mask Internal IRQ7: 0 = Disable; 1 = Enable. Reserved: Set to 0. Mask Internal IRQ5: 0 = Disable; 1 = Enable. Mask Internal IRQ4: 0 = Disable; 1 = Enable. Mask Internal IRQ3: 0 = Disable; 1 = Enable. Reserved: Set to 0.
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Offset 20h Description Audio Bus Master 0 Command Register (R/W) Reset Value = 00h
Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master 0. 0 = PCI reads performed; 1 = PCI writes performed. This bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master 0. 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must either be paused or reach EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior; including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 21h Audio Bus Master 0 SMI Status Register (RC) Reset Value = 00h
Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. Offset 22h-23h Offset 24h-27h Reserved Audio Bus Master 0 PRD Table Address (R/W) Reset Value = xxh Reset Value = 00000000h
Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 0. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 0 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Offset 28h Reserved: Set to 0. Audio Bus Master 1 Command Register (R/W) Reset Value = 00h
Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master 1. 0 = PCI reads performed; 1 = PCI writes performed. This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master 1. 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE.
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Register Descriptions (Continued)
Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Offset 29h Description Audio Bus Master 1 SMI Status Register (RC) Reset Value = 00h
Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:2 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. Offset 2Ah-2Bh Offset 2Ch-2Fh Reserved Audio Bus Master 1 PRD Table Address (R/W) Reset Value = xxh Reset Value = 00000000h
Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 1. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 1 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Offset 30h Reserved: Set to 0. Audio Bus Master 2 Command Register (R/W) Reset Value = 00h
Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master 2. 0 = PCI reads performed; 1 = PCI writes performed. This bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master 2. 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 31h Audio Bus Master 2 SMI Status Register (RC) Reset Value = 00h
Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. 7:4 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. Offset 32h-33h Offset 34h-37h Reserved Audio Bus Master 2 PRD Table Address (R/W) Reset Value = xxh Reset Value = 00000000h
Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5. 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 2. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 2 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0.
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Offset 38h Description Audio Bus Master 3 Command Register (R/W) Reset Value = 00h
Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master 3. 0 = PCI reads performed; 1 = PCI writes performed. This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master 3. 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 39h Audio Bus Master 3 SMI Status Register (RC) Reset Value = 00h
Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 7:4 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. Offset 3Ah-3Bh Offset 3Ch-3Fh Reserved Audio Bus Master 3 PRD Table Address (R/W) Reset Value = xxh Reset Value = 00000000h
Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 3. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 3 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Offset 40h Reserved: Set to 0. Audio Bus Master 4 Command Register (R/W) Reset Value = 00h
Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master 4. 0 = PCI reads performed; 1 = PCI writes performed. This bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master 4. 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE.
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Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)
Bit Offset 41h Description Audio Bus Master 4 SMI Status Register (RC) Reset Value = 00h
Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). 7:4 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. Offset 42h-43h Offset 44h-47h Reserved Audio Bus Master 4 PRD Table Address (R/W) Reset Value = xxh Reset Value = 00000000h
Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot). 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 4. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 4 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Offset 48h Reserved: Set to 0. Audio Bus Master 5 Command Register (R/W) Reset Value = 00h
Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). 7:4 3 Reserved: Set to 0. Must return 0 on reads. Read or Write Control: Set the transfer direction of Audio Bus Master 5. 0 = PCI reads performed; 1 = PCI writes performed. This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 0 Reserved: Set to 0. Must return 0 on reads. Bus Master Control: Controls the state of the Audio Bus Master 5. 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. Offset 49h Audio Bus Master 5 SMI Status Register (RC) Reset Value = 00h
Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). 7:4 1 Reserved (Read to Clear) Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first? 0 = No; 1 = Yes. If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0 = No; 1 = Yes.
Note: Must be read and written as a BYTE. Offset 4Ah-4Bh Offset 4Ch-4Fh Reserved Audio Bus Master 5 PRD Table Address (R/W) Reset Value = xxh Reset Value = 00000000h
Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot). 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 5. When written, this register points to the first entry in a PRD table. Once Audio Bus Master 5 is enabled (Command Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Reserved Reset Value = xxh
Offset 50h-FFh
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4.3.5 Video Controller Registers - Function 4 The register space for the video controller is divided into two sections. The first section is used to configure the PCI portion of the controller. A Base Address Register at F4 Index 10h (F4BAR) points to the base address of where the second portion of the register space is located. The second section contains the registers used by the video controller to carry out video operations. Table 4-22 shows the PCI header registers of F4. The memory mapped registers accessed through F4BAR, and shown in Table 4-23, must be accessed using DWORD operations. When writing to one of these 32-bit registers, all four bytes must be written. If the F4 Video Configuration Trap bit (F0 Index 42h[1]) is set, access to the PCI header registers causes an SMI. Access through F4BAR is not affected by this bit.
Table 4-22. F4 Index xxh: PCI Header Registers for Video Controller Configuration
Bit Description Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) Reset Value = 1078h Reset Value = 0104h Reset Value = 0000h
Index 00h-01h Index 02h-03h Index 04h-05h 15:2 1 0 Reserved (Read Only)
Memory Space: Allow CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable. This bit must be enabled to access memory offsets through F4BAR (F4 Index 10h). Reserved (Read Only) PCI Status Register (RO) Device Revision ID Register (RO) PCI Class Code Register (RO) PCI Cache Line Size Register (RO) PCI Latency Timer Register (RO) PCI Header Type (RO) PCI BIST Register (RO) Base Address Register - F4BAR (R/W) Reset Value = 0280h Reset Value = 00h Reset Value = 030000h Reset Value = 00h Reset Value = 00h Reset Value = 00h Reset Value = 00h Reset Value = 00000000h
Index 06h-07h Index 08h Index 09h-0Bh Index 0Ch Index 0Dh Index 0Eh Index 0Fh Index 10h-13h
This register sets the base address of the memory mapped video controller registers. Bits [11:0] are read only (0000 0000 0000), indicating a 4 KB memory address range. Refer to Table 4-23 for the video controller register bit formats and reset values. 31:12 11:0 Video Controller and Clock Control Base I/O Address Address Range (Read Only) Reserved Reserved Reset Value = 00h Reset Value = xxh
Index 14h-3Fh Index 40h-FFh
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Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers
Bit Description Video Configuration Register (R/W) Reset Value = 00000000h
Offset 00h-03h 31 30 29 Reserved: Set to 0
High Speed Timing for Video Interface: High speed timings for the video interface. 0 = Disable; 1= Enable. If bit 30 is enabled, bit 25 should be set to 0. 16-bit Video Interface: Allow video interface to be 16 bits. 0 = Disable; 1= Enable. If bit 29 is enabled, 8 bits of pixel data is used for video. The 24-bit pixel data is then dithered to 16 bits. Note: F4BAR+Memory Offset 04h[25] should be set to the same value as this bit (bit 29).
28
YUV 4:2:2 or 4:2:0 Mode: 0 = 4:2:2 mode; 1= 4:2:0 mode. If 4:2:0 mode is selected, bits [3:2] should be set to 01 for 8-bit video mode and 10 for 16-bit video mode. Note: The GX-series processor does not support 4:2:0 mode.
27 26 25
Video Line Size (DWORDs): This is the MSB of the Video Line Size (DWORDs). See bits [15:8] for description. Reserved: Set to 0 Early Video Ready: Generate VID_RDY output signal one-half VID_CLK period early to improve the speed of the video port operation. 0 = Disable; 1 = Enable. If bit 30 is enabled, this bit (bit 25) should be set to 0. Initial Buffer Read Address: This is the MSB of the Initial Buffer Read Address. See bits [23:16] for description. Initial Buffer Read Address: This field is used to preload the starting read address for the line buffers at the beginning of each display line. It is used for hardware clipping of the video window at the left edge of the active display. It represents the DWORD address of the source pixel which is to be displayed first. For an unclipped window, this value should be 0. Video Line Size (DWORDs): This field represents the horizontal size of the source video data in DWORDs. Y Filter Enable: Vertical filter. 0 = Disable; 1= Enable. X Filter Enable: Horizontal filter. 0 = Disable; 1 = Enable. CSC Bypass: Allows color-space-converter to be bypassed. Primarily used for displaying an RGB graphics overlay rather than a YUV video overlay. 0 = Overlay data passes through CSC; 1 = Overlay data bypasses CSC. GV Select: Selects whether graphics or video data will be passed through the scaler hardware. 0 = Video data; 1 = Graphics data. Video Input Format: This field defines the byte ordering of the video data on the VID_DATA bus. 8-Bit Mode (Value Byte Order [0:3]) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 01 = Y1 V Y0 U or 4:2:0 10 = Y0 U Y1 V 11 = Y0 V Y1 U Note: U = Cb, V = Cr 16-Bit Mode (Value Byte Order [0:3]) 00 = U Y0 V Y1 (also used for RGB 5:6:5 input) 01 = Y0 U Y1 V 10 = Y1 V Y0 U or 4:2:0 11 = Reserved
24 23:16
15:8 7 6 5 4 3:2
If bit 28 is set for 4:2:0 mode, these bits (bits [3:2]) should be set to 01 for 8-bit video mode and 10 for 16-bit video mode. 1 0 Video Register Update: Allow video position and scale registers to be updated simultaneously on next occurrence of vertical sync. 0 = Disable; 1 = Enable. Video Enable: Video acceleration hardware. 0 = Disable; 1 = Enable.
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Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued)
Bit Description Display Configuration Register (R/W) Reset Value = 00000000h
Offset 04h-07h 31 30:28 27 26 25 24 23 22 21 20 19:17 16:14
DDC Input Data (Read Only): This is the DDC input data bit for reads. Reserved: Set to 0. Flat Panel On (Read Only): This bit indicates whether the attached flat panel display is powered on or off. The bit transitions at the end of the power-up or power-down sequence. 0 = Off; 1 = On. Reserved: Set to 0. 16-Bit Graphics Enable: This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset 00h[29]. This bit should be set to the same value as the 16-bit Video Interface bit. DDC Output Enable: This bit enables the DDC_SDA line to be driven for write data. 0 = DDC_SDA (pin M4) is an input; 1 = DDC_SDA (pin M4) is an output. DDC Output Data: This is the DDC data bit. DDC Clock: This is the DDC clock bit. It is used to clock the DDC_SDA bit. Palette Bypass: Selects whether graphics or video data should bypass the gamma RAM. 0 = Video data; 1 = Graphics data. Video/Graphics Color Key Select: Selects whether the video or graphics data stream will be used for color/chroma keying. 0 = Graphics data is compared to color key; 1 = Video data is compared to color key. Power Sequence Delay: This field selects the number of frame periods that transpire between successive transitions of the power sequence control lines. Valid values are 001 to 111. CRT Sync Skew: This 3-bit field represents the number of pixel clocks to skew the horizontal and vertical syncs that are sent to the CRT. This field should be programmed to 100 as the baseline. The syncs may be moved forward or backward relative to the pixel data via this register. It is used to compensate for the pipeline delay through the graphics pipeline. Flat Panel Dither Enable: This bit enables flat panel dithering. It enables 24 bpp display data to be approximated with an 18-bit flat panel display. 0 = Disable; 1 = Enable. XGA Flat Panel: This bit enables the FP_CLK_ EVEN output signal which can be used to demultiplex the FP_DATA bus into even and odd pixels. 0 = Standard flat panel; 1 = XGA flat panel. Flat Panel Vertical Synchronization Polarity: Selects the flat panel vertical sync polarity. 0 = FP vertical sync is normally low, transitioning high during sync interval. 1 = FP vertical sync is normally high, transitioning low during sync interval. Flat Panel Horizontal Synchronization Polarity: Selects the flat panel horizontal sync polarity. 0 = FP horizontal sync is normally low, transitioning high during sync interval. 1 = FP horizontal sync is normally high, transitioning low during sync interval. CRT Vertical Synchronization Polarity: Selects the CRT vertical sync polarity. 0 = CRT vertical sync is normally low, transitioning high during sync interval. 1 = CRT vertical sync is normally high, transitioning low during sync interval.
13 12 11
10
9
8
CRT Horizontal Synchronization Polarity: Selects the CRT horizontal sync polarity. 0 = CRT horizontal sync is normally low, transitioning high during sync interval. 1 = CRT horizontal sync is normally high, transitioning low during sync interval. Flat Panel Data Enable: Enables the flat panel data bus. 0 = FP_DATA [17:0] is forced low; 1 = FP_DATA [17:0] is driven based upon power sequence control. Flat Panel Power Enable: The transition of this bit initiates a flat panel power-up or power-down sequence. 0 -> 1 = Power-up flat panel; 1 -> 0 = Power-down flat panel. DAC Power-Down (active low): This bit must be set to power-up the video DACs. It can be cleared to power-down the video DACs when not in use. 0 = DACs are powered down; 1 = DACs are powered up. Reserved: Set to 0. DAC Blank Enable: This bit enables the blank to the video DACs. 0 = DACs are constantly blanked; 1 = DACs are blanked normally. CRT Vertical Sync Enable: Enables the CRT vertical sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. CRT Horizontal Sync Enable: Enables the CRT horizontal sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable. Display Enable: Enables the graphics display pipeline. It is used as a reset for the display control logic. 0 = Reset display control logic; 1 = Enable display control logic.
7
6
5 4 3 2 1 0
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Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued)
Bit Description Video X Register (R/W) Reset Value = xxxxxxxxh
Offset 08h-0Bh 31:27 26:16 15:11 10:0 Reserved: Set to 0.
Video X End Position: This field represents the horizontal end position of the video window according to the following formula. Position programmed = screen position + (H_TOTAL - H_SYNC_END) - 13. Reserved: Set to 0. Video X Start Position: This field represents the horizontal start position of the video window according to the following formula. Position programmed = screen position + (H_TOTAL - H_SYNC_END) - 13. Video Y Register (R/W) Reset Value = xxxxxxxxh
Offset 0Ch-0Fh 31:27 26:16 15:11 10:0 Reserved: Set to 0.
Video Y End Position: This field represents the vertical end position of the video window according to the following formula. Position programmed = screen position + (V_TOTAL - V_SYNC_END) + 1. Reserved: Set to 0. Video Y Start Position: This field represents the vertical start position of the video window according to the following formula. Position programmed = screen position + (V_TOTAL - V_SYNC_END) + 1. Video Scale Register (R/W) Reset Value = xxxxxxxxh
Offset 10h-13h 31:30 29:16 Reserved: Set to 0.
Video Y Scale Factor: This field represents the video window vertical scale factor according to the following formula. VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1) Where: Ys = Video source vertical size in lines Yd = Video destination vertical size in lines
15:14 13:0
Reserved: Set to 0. Video X Scale Factor: This field represents the video window horizontal scale factor according to the following formula. VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1) Where: Xs = Video source horizontal size in pixels Xd = Video destination horizontal size in pixels
Offset 14h-17h 31:24 23:0 Reserved: Set to 0.
Video Color Key Register (R/W)
Reset Value = xxxxxxxxh
Video Color Key: This field represents the video color key. It is a 24-bit RGB value. The graphics or video data being compared may be masked prior to the compare by programming the Video Color Mask Register (F4BAR+Memory Offset 18h) appropriately. Video Color Mask Register (R/W) Reset Value = xxxxxxxxh
Offset 18h-1Bh 31:24 23:0 Reserved: Set to 0.
Video Color Mask: This field represents the video color mask. It is a 24-bit RGB value. Zeroes in the mask cause the corresponding bits in the graphics or video stream being compared to be ignored. Palette Address Register (R/W) Reset Value = xxxxxxxxh
Offset 1Ch-1Fh 31:8 7:0 Reserved: Set to 0.
Palette Address: The value programmed is used to initialize the palette address counter. Palette Data Register (R/W) Reset Value = xxxxxxxxh
Offset 20h-23h 31:24 23:0 Reserved: Set to 0.
Palette Data: This register contains the read or write data for a Gamma RAM access.
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Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued)
Bit Description DOT Clock Configuration Register (R/W) Reset Value = 00000000h
Offset 24h-27h 31 30
Feedback Reset: Reset the PLL postscaler and feedback divider. 0 = Normal operation; 1 = Reset. A more comprehensive reset description is provided in bit 8. Half Clock: 0 = Enable; 1 = Disable. For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post divider output to more closely approximate a 50% output duty cycle.
29 28:24
Reserved: Set to 0. 5-Bit DCLK PLL Post Divisor (PD) Value: Selects value of 1 to 31. 00000 = PD divisor of 8 00001 = PD divisor of 6 00010 = PD divisor of 18 00011 = PD divisor of 4 00100 = PD divisor of 12 00101 = PD divisor of 16 00110 = PD divisor of 24 00111 = PD divisor of 2 *See bit 11 description. 01000 = PD divisor of 10 01001 = PD divisor of 20 01010 = PD divisor of 14 01011 = PD divisor of 26 01100 = PD divisor of 22 01101 = PD divisor of 28 01110 = PD divisor of 30 01111 = PD divisor of 1* 10000 = PD divisor of 9 10001 = PD divisor of 7 10010 = PD divisor of 19 10011 = PD divisor of 5 10100 = PD divisor of 13 10101 = PD divisor of 17 10110 = PD divisor of 25 10111 = PD divisor of 3 11000 = PD divisor of 11 11001 = PD divisor of 21 11010 = PD divisor of 15 11011 = PD divisor of 27 11100 = PD divisor of 23 11101 = PD divisor of 29 11110 = PD divisor of 31 11111 = Reserved
23 22:12 11 10 9 8
Plus 1 (+1): Adds 1 or 0 to FD (DCLK PLL VCO Feedback Divisor) parameter in equation (see Note). 0 = Add 0 to FD; 1 = Add 1 to FD. N: This bit represents "N" in the equation (see Note). It is used to solve the value of FD (DCLK PLL VCO feedback divisor). N can be a value of 1 to 400. For all values of N, refer to Table 4-24 on page 209. CLK_ON: 0 = PLL disable; 1 = PLL enable. If PD = 1 (i.e., bits [28:24] = 01111) the PLL is always enabled and cannot be disabled by this bit. DOT Clock Select: 0 = DCLK; 1 = TV_CLK. Reserved: Set to 0 Bypass PLL: Connects the input of the PLL directly to the output of the PLL. 0 = Normal Operation; 1 = Bypass PLL. If this bit is set to 1, the input of the PLL bypasses the PLL and resets the VCO control voltage, which in turn powers down the PLL. Allow 0.5 ms for the control voltage to be driven to 0V.
7:6 5 4:3 2:0
Reserved: Set to 0. Reserved (Read Only): Write as read Reserved: Set to 0. PLL Input Divide (ID) Value: Selects value of 2 to 9 (see Note). 000 = ID divisor of 2 010 = ID divisor of 4 100 = ID divisor of 6 110 = ID divisor of 8 001 = ID divisor of 3 011 = ID divisor of 5 101 = ID divisor of 7 111 = ID divisor of 9
Note:
To calculate DCLK output frequency: Equation #1: DCLK = [CLK_14MHZ * FD] / [PD *ID] Condition: 140 MHz < [DCLK * PD] < 300 MHz Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3 PD is derived from bits [28:24] ID is derived from bits [2:0]
Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 is achieved by clearing bit 23 to 0.
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Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued)
Bit Description CRC Signature and TFT/TV Configuration Register (R/W) Reset Value = 00000100h
Offset 28h-2Bh 31:8 7 6 5 4 3 2
24-Bit Video Signature Data (Read Only) SYNC Override: Drive VSYNC_OUT on FP_VSYNC_OUT and HSYNC_OUT on FP_HSYNC_OUT. 0 = Disable; 1 = Enable. Invert FP_CLK: 0 = Disable; 1 = Enable. (Applicable for TV not TFT.) Invert FP_CLK_EVEN: 0 = Disable; 1 = Enable. Reserved (Read Only) Signature Source Select: 0 = RGB data; 1 = FP data. (FP data occupies the top 6 bits of each color byte to the signature, with the bottom two bits always zero.) Signature Free Run: 0 = Disable; 1 = Enable. When high, with the signature enabled, the signature generator captures data continuously across multiple frames. This bit may be set high when the signature is started, then later set low, which causes the signature generation process to stop at the end of the current frame.
1
FP_HSYNC_OUT Delay: 0 = Disable; 1 = Enable. (Applicable for TFT not TV.) When SYNC Override (bit 7) is high, this bit (bit 1) can be set high to delay FP_HSYNC_OUT by an extra two clock cycles. When the SYNC Override (bit 7) is low, this bit should also be set low.
0
Signature Enable: 0 = Disable; 1= Enable. When low, the signature register is reset to 000001h and held (no capture). When high, the signature register captures the pixel data signature with each pixel clock beginning with the next vsync.
Offset 2Ch-FFh
Reserved
Reset Value = xxh
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Register Descriptions (Continued)
Table 4-24. F4BAR+Memory Offset 24h[22:12] Decode (Value of "N")
N 400 399 398 397 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 Reg. Value 33A 674 4E8 1D0 3A0 740 681 502 205 40B 16 2D 5B B7 16F 2DE 5BD 37B 6F6 5EC 3D9 7B2 765 6CB 596 32D 65A 4B4 168 2D0 5A1 343 686 50C 219 433 66 CD 19B 336 66C 4D8 1B0 360 6C0 580 301 602 404 8 11 N 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 Reg. Value 23 47 8F 11F 23E 47D FA 1F5 3EA 7D4 7A9 753 6A7 54E 29D 53B 277 4EF 1DE 3BC 778 6F1 5E2 3C5 78A 715 62B 456 AC 159 2B2 565 2CB 597 32F 65E 4BC 178 2F0 5E1 3C3 786 70D 61B 436 6C D9 1B3 366 6CC 598 N 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 Reg. Value 331 662 4C4 188 310 620 440 80 101 202 405 A 15 2B 57 AF 15F 2BE 57D 2FB 5F7 3EF 7DE 7BD 77B 6F7 5EE 3DD 7BA 775 6EB 5D6 3AD 75A 6B5 56A 2D5 5AB 357 6AE 55C 2B9 573 2E7 5CF 39F 73E 67D 4FA 1F4 3E8 N 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 Reg. Value 7D0 7A1 743 687 50E 21D 43B 76 ED 1DB 3B6 76C 6D9 5B2 365 6CA 594 329 652 4A4 148 290 521 243 487 10E 21C 439 72 E5 1CB 396 72C 659 4B2 164 2C8 591 323 646 48C 118 230 461 C2 185 30A 614 428 50 A1 N 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 Reg. Value 143 286 50D 21B 437 6E DD 1BB 376 6EC 5D8 3B1 762 6C5 58A 315 62A 454 A8 151 2A2 545 28B 517 22F 45F BE 17D 2FA 5F5 3EB 7D6 7AD 75B 6B7 56E 2DD 5BB 377 6EE 5DC 3B9 772 6E5 5CA 395 72A 655 4AA 154 2A8 N 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 Reg. Value 551 2A3 547 28F 51F 23F 47F FE 1FD 3FA 7F4 7E9 7D3 7A7 74F 69F 53E 27D 4FB 1F6 3EC 7D8 7B1 763 6C7 58E 31D 63A 474 E8 1D1 3A2 744 689 512 225 44B 96 12D 25A 4B5 16A 2D4 5A9 353 6A6 54C 299 533 267 4CF N 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Reg. Value 19E 33C 678 4F0 1E0 3C0 780 701 603 406 C 19 33 67 CF 19F 33E 67C 4F8 1F0 3E0 7C0 781 703 607 40E 1C 39 73 E7 1CF 39E 73C 679 4F2 1E4 3C8 790 721 643 486 10C 218 431 62 C5 18B 316 62C 458 B0 N 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reg. Value 161 2C2 585 30B 616 42C 58 B1 163 2C6 58D 31B 636 46C D8 1B1 362 6C4 588 311 622 444 88 111 222 445 8A 115 22A 455 AA 155 2AA 555 2AB 557 2AF 55F 2BF 57F 2FF 5FF 3FF
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4.4 USB REGISTERS
dard Index and Byte-Enable method. Registers marked as "Reserved", and reserved bits within a register, should not be changed by software. In the PCI Configuration space, there is one Base Address Register (BAR), at Index 10h, which is used to map the USB Host Controller's operational register set into a 4K memory space. Once the BAR register has been initialized, and the PCI Command register at Index 04h has been set to enable the Memory space decoder, these "USB Controller" registers are accessible. The memory-mapped USB Controller Registers are listed in Table 4-26. They follow the Open Host Controller Interface (OHCI) specification. The USB Host Controller exists logically as its own PCI "Device", separate from the Chipset functions. It is a singlefunction device, and so it contains a PCI Configuration space for only Function 0. Depending on the state of the HOLD_REQ# pin on reset, the USB Controller will respond to one of two Device numbers for access to its PCI Configuration registers: HOLD_REQ# low: Responds to pin AD29 high (Device 13h in a Geode system). HOLD_REQ# high: Responds to pin AD27 high (Device 11h in a Geode system). The PCI Configuration registers are listed in Table 4-25. They can be accessed as any number of bytes within a single 32-bit aligned unit. They are selected by the PCI-stan-
Table 4-25. USB Index xxh: USB PCI Configuration Registers
Bit Description Vendor Identification Register (RO) Device Identification Register (RO) Command Register (R/W) Reset Value = 0E11h Reset Value = A0F8h Reset Value = 0000h
Index 00h-01h Index 02h-03h Index 04h-05h 15:10 9 8 7 6 5 4 Reserved: Set to 0.
Fast Back-to-Back Enable (Read Only): USB only acts as a master to a single device, so this functionality is not needed. It is always disabled (must always be set to 0). SERR#: USB asserts SERR# when it detects an address parity error. 0 = Disable; 1 = Enable. Wait Cycle Control: USB does not need to insert a wait state between the address and data on the AD lines. It is always disabled (bit is set to 0). Parity Error: USB asserts PERR# when it is the agent receiving data and it detects a data parity error. 0 = Disable; 1 = Enable. VGA Palette Snoop Enable (Read Only): USB does not support this function. It is always disabled (bit is set to 0). Memory Write and Invalidate: Allow USB to run Memory Write and Invalidate commands. 0 = Disable; 1 = Enable. The Memory Write and Invalidate command will only occur if the cache line size is set to 32 bytes and the memory write is exactly one cache line. If the CS5530A is being used in a GX-series processor based system, this bit must be set to 0.
3 2 1 0
Special Cycles: USB does not run special cycles on PCI. It is always disabled (bit is set to 0). PCI Master Enable: Allow USB to run PCI master cycles. 0 = Disable; 1 = Enable. Memory Space: Allow USB to respond as a target to memory cycles. 0 = Disable; 1 = Enable. I/O Space: Allow USB to respond as a target to I/O cycles. 0 = Disable; 1 = Enable.
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Table 4-25. USB Index xxh: USB PCI Configuration Registers (Continued)
Bit Description Status Register (R/W) Reset Value = 0280h
Index 06h-07h 15 14 13 12 11 10:9 8 7 6:0
Detected Parity Error: This bit is set whenever the USB detects a parity error, even if the Parity Error (response) detection enable bit (PCIUSB 04h[6]) is disabled. Write 1 to clear. SERR# Status: This bit is set whenever the USB detects a PCI address error. Write 1 to clear. Received Master Abort Status: This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory cycle. Write 1 to clear. Received Target Abort Status: This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted by a PCI target. Write 1 to clear. Signaled Target Abort Status: This bit is set whenever the USB signals a target abort. Write 1 to clear. DEVSEL# Timing (Read Only): These bits indicate the DEVSEL# timing when performing a positive decode. Since DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b. Data Parity Reported: Set to 1 if the Parity Error Response bit (Command Register bit 6) is set, and USB detects PERR# asserted while acting as PCI master (whether PERR# was driven by USB or not). Fast Back-to-Back Capable (Read Only): USB does support fast back-to-back transactions when the transactions are not to the same agent. This bit is always 1. Reserved: Set to 0.
Note: The PCI specification defines this register to record status information for PCI related events. This is a read/write register. However, writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location is a 1. Index 08h Index 09h-0Bh Device Revision ID Register (RO) PCI Class Code Register (RO) Reset Value = 06h Reset Value = 0C0310h
This register identifies this function as an OpenHCI device. The base class is 0Ch (serial bus controller). The sub class is 03h (universal serial bus). The programming interface is 10h (OpenHCI). Index 0Ch Cache Line Size Register (R/W) Reset Value = 00h
This register identifies the system cache line size in units of 32-bit WORDs. The USB only stores the value of bit 3 in this register since the cache line size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register is read back as 00h. In a CS5530A/GX-series processor based system this register must be set to 00h since the GX-series processor has a 16-byte cache line size. Index 0Dh Latency Timer Register (R/W) Reset Value = 00h
This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles. Index 0Eh Header Type Register (RO) Reset Value = 00h
This register identifies the type of the predefined header in the configuration space. Since the USB is a single function device and not a PCI-to-PCI bridge, this byte should be read as 00h. Index 0Fh BIST Register (RO) Reset Value = 00h
This register identifies the control and status of Built In Self Test. The USB does not implement BIST, so this register is read only. Index 10h-13h Base Address Register (R/W) Reset Value = 00000000h
This BAR sets the base address of the memory mapped USB controller registers. Bits [11:0] are read only (0000 0000 0000), indicating a 4 KB memory address range. Refer to Table 4-26 for the USB controller register bit formats and reset values. 31:12 11:0 USB Controller Base Address Address Range (Read Only) Reserved Interrupt Line Register (R/W) Reset Value = xxh Reset Value = 00h
Index 14h-3Bh Index 3Ch
This register identifies which of the system interrupt controllers the devices interrupt pin is connected to. The value of this register is used by device drivers and has no direct meaning to the USB. Index 3Dh Interrupt Pin Register (RO) Reset Value = 01h
This register identifies which interrupt pin a device uses. Since the USB uses INTA#, this value is set to 01h.
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Table 4-25. USB Index xxh: USB PCI Configuration Registers (Continued)
Bit Index 3Eh Description Min. Grant Register (RO) Reset Value = 00h
This register specifies the desired settings for how long of a burst the USB needs assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Index 3Fh Max. Latency Register (RO) Reset Value = 50h
This register specifies the desired settings for how often the USB needs access to the PCI bus assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Index 40h-43h ASIC Test Mode Enable Register (R/W) Reset Value = 000F0000h
Used for internal debug and test purposes only. Index 44h-45h 15:9 8 Reserved: Read/Write 0s. SIE Pipeline Disable: When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor. This is a fail-safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz. Write Only: Read as 0s. Data Buffer Region 16: When set, the size of the region for the data buffer is 16 bytes. Otherwise, the size is 32 bytes. Reserved Reserved Reset Value = 00h Reset Value = xxh ASIC Operational Mode Enable Register (R/W) Reset Value = 0000h
7:1 0
Index 46h-47h Index 48h-FFh
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers
Bit Description HcRevision Register (RO) Reset Value = 00000110h
Offset 00h-03h 31:8 7:0 Reserved: Read/Write 0s.
Revision (Read Only): Indicates the Open HCI Specification revision number implemented by the Hardware. USB supports 1.0 specification. (X.Y = XYh). HcControl Register (R/W) Reset Value = 00000000h
Offset 04h-07h 31:11 10 9 8 7:6 Reserved: Read/Write 0s.
RemoteWakeupConnectedEnable: If a remote wakeup signal is supported, this bit enables that operation. Since there is no remote wakeup signal supported, this bit is ignored. RemoteWakeupConnected (Read Only): This bit indicated whether the HC supports a remote wakeup signal. This implementation does not support any such signal. The bit is hard-coded to 0. InterruptRouting: This bit is used for interrupt routing: 0 = Interrupts routed to normal interrupt mechanism (INT); 1 = Interrupts routed to SMI. HostControllerFunctionalState: This field sets the HC state. The HC may force a state change from UsbSuspend to UsbResume after detecting resume signaling from a downstream port. States are: 00 = UsbReset 01 = UsbResume 10 = UsbOperational 11 = UsbSuspend
5 4 3 2 1:0
BulkListEnable: When set, this bit enables processing of the Bulk list. ControlListEnable: When set, this bit enables processing of the Control list. IsochronousEnable: When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). While processing the Periodic List, the HC will check this bit when it finds an isochronous ED. PeriodicListEnable: When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The HC checks this bit prior to attempting any periodic transfers in a frame. ControlBulkServiceRatio: Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1 where N is the number of Control Endpoints (i.e., 00 = 1 Control Endpoint; 11 = 3 Control Endpoints). HcCommandStatus Register (R/W) Reset Value = 00000000h
Offset 08h-0Bh 31:18 17:16 15:4 3 2 1 0 Reserved: Read/Write 0s.
ScheduleOverrunCount: This field increments every time the SchedulingOverrun bit in HcInterruptStatus is set. The count wraps from 11 to 00. Reserved: Read/Write 0s. OwnershipChangeRequest: When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit is cleared by software. BulkListFilled: Set to indicate there is an active ED on the Bulk List. The bit may be set by either software or the HC and cleared by the HC each time it begins processing the head of the Bulk List. ControlListFilled: Set to indicate there is an active ED on the Control List. It may be set by either software or the HC and cleared by the HC each time it begins processing the head of the Control List. HostControllerReset: This bit is set to initiate a software reset. This bit is cleared by the HC upon completion of the reset operation. HcInterruptStatus Register (R/W) Reset Value = 00000000h
Offset 0Ch-0Fh 31 30 29:7 6 5 4 3 2 1 0 Reserved: Read/Write 0s.
OwnershipChange: This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. Reserved: Read/Write 0s. RootHubStatusChange: This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed. FrameNumberOverflow: Set when bit 15 of FrameNumber changes value. UnrecoverableError (Read Only): This event is not implemented and is hard-coded to 0. Writes are ignored. ResumeDetected: Set when HC detects resume signaling on a downstream port. StartOfFrame: Set when the Frame Management block signals a Start of Frame event. WritebackDoneHead: Set after the HC has written HcDoneHead to HccaDoneHead. SchedulingOverrun: Set when the List Processor determines a Schedule Overrun has occurred.
Note: All bits are set by hardware and cleared by software.
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)
Bit Description HcInterruptEnable Register (R/W) Reset Value = 00000000h
Offset 10h-13h 31 30 29:7 6 5 4 3 2 1 0
MasterInterruptEnable: This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific enable bits listed above. OwnershipChangeEnable: 0 = Ignore; 1 = Enable interrupt generation due to Ownership Change. Reserved: Read/Write 0s. RootHubStatusChangeEnable: 0 = Ignore; 1 = Enable interrupt generation due to Root Hub Status Change. FrameNumberOverflowEnable: 0 = Ignore; 1 = Enable interrupt generation due to Frame Number Overflow. UnrecoverableErrorEnable: This event is not implemented. All writes to this bit are ignored. ResumeDetectedEnable: 0 = Ignore; 1 = Enable interrupt generation due to Resume Detected. StartOfFrameEnable: 0 = Ignore; 1 = Enable interrupt generation due to Start of Frame. WritebackDoneHeadEnable: 0 = Ignore; 1 = Enable interrupt generation due to Writeback Done Head. SchedulingOverrunEnable: 0 = Ignore; 1 = Enable interrupt generation due to Scheduling Overrun.
Note: Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged. Offset 14h-17h 31 30 29:7 6 5 4 3 2 1 0 HcInterruptDisable Register (R/W) Reset Value = C000006Fh
MasterInterruptEnable: Global interrupt disable. A write of 1 disables all interrupts. OwnershipChangeEnable: 0 = Ignore; 1 = Disable interrupt generation due to Ownership Change. Reserved: Read/Write 0s. RootHubStatusChangeEnable: 0 = Ignore; 1 = Disable interrupt generation due to Root Hub Status Change. FrameNumberOverflowEnable: 0 = Ignore; 1 = Disable interrupt generation due to Frame Number Overflow. UnrecoverableErrorEnable: This event is not implemented. All writes to this bit will be ignored. ResumeDetectedEnable: 0 = Ignore; 1 = Disable interrupt generation due to Resume Detected. StartOfFrameEnable: 0 = Ignore; 1 = Disable interrupt generation due to Start of Frame. WritebackDoneHeadEnable: 0 = Ignore; 1 = Disable interrupt generation due to Writeback Done Head. SchedulingOverrunEnable: 0 = Ignore; 1 = Disable interrupt generation due to Scheduling Overrun.
Note: Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 to a bit leaves the bit unchanged. Offset 18h-1Bh 31:8 7:0 HCCA: Pointer to HCCA base address. Reserved: Read/Write 0s. HcPeriodCurrentED Register (R/W) Reset Value = 00000000h HcHCCA Register (R/W) Reset Value = 00000000h
Offset 1Ch-1Ch 31:4 3:0
PeriodCurrentED: Pointer to the current Periodic List ED. Reserved: Read/Write 0s. HcControlHeadED Register (R/W) Reset Value = 00000000h
Offset 20h-23h 31:4 3:0
ControlHeadED: Pointer to the Control List Head ED. Reserved: Read/Write 0s. HcControlCurrentED Register (R/W) Reset Value = 00000000h
Offset 24h-27h 31:4 3:0
ControlCurrentED: Pointer to the current Control List ED. Reserved: Read/Write 0s. HcBulkHeadED Register (R/W) Reset Value = 00000000h
Offset 28h-2Bh 31:4 3:0
BulkHeadED: Pointer to the Bulk List Head ED. Reserved: Read/Write 0s. HcBulkCurrentED Register (R/W) Reset Value = 00000000h
Offset 2Ch-2Fh 31:4 3:0
BulkCurrentED: Pointer to the current Bulk List ED. Reserved: Read/Write 0s. HcDoneHead Register (R/W) Reset Value = 00000000h
Offset 30h-33h 31:4 3:0
DoneHead: Pointer to the current Done List Head ED. Reserved: Read/Write 0s.
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)
Bit Description HcFmInterval Register (R/W) Reset Value = 00002EDFh
Offset 34h-37h 31 30:16 15:14 13:0
FrameIntervalToggle (Read Only): This bit is toggled by HCD when it loads a new value into FrameInterval. FSLargestDataPacket (Read Only): This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. Reserved: Read/Write 0s. FrameInterval: This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. HcFrameRemaining Register (RO) Reset Value = 00002Exxh
Offset 38h-3Bh 31 30:14 13:0
FrameRemainingToggle (Read Only): Loaded with FrameIntervalToggle when FrameRemaining is loaded. Reserved: Read 0s. FrameRemaining (Read Only): When the HC is in the UsbOperational state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with FrameInterval. In addition, the counter loads when the HC transitions into UsbOperational. HcFmNumber Register (RO) Reset Value = 00000000h
Offset 3Ch-3Fh 31:16 15:0 Reserved: Read 0s.
FrameNumber (Read Only): This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining. The count rolls over from FFFFh to 0h. HcPeriodicStart Register (R/W) Reset Value = 00000000h
Offset 40h-43h 31:14 13:0 Reserved: Read/Write 0s.
PeriodicStart: This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. HcLSThreshold Register (R/W) Reset Value = 00000628h
Offset 44h-47h 31:12 11:0 Reserved: Read/Write 0s.
LSThreshold: This field contains a value used by the Frame Management block to determine whether or not a low speed transaction can be started in the current frame. HcRhDescriptorA Register (R/W) Reset Value = 01000002h
Offset 48h-4Bh 31:24
PowerOnToPowerGoodTime: This field value is represented as the number of 2 ms intervals, ensuring that the power switching is effective within 2 ms. Only bits [25:24] are implemented as R/W. The remaining bits are read only as 0. It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided. This field should be written to support system implementation. This field should always be written to a non-zero value. Reserved: Read/Write 0s. NoOverCurrentProtection: This bit should be written to support the external system port over-current implementation. 0 = Over-current status is reported; 1 = Over-current status is not reported. OverCurrentProtectionMode: This bit should be written 0 and is only valid when NoOverCurrentProtection is cleared. 0 = Global Over-Current; 1 = Individual Over-Current DeviceType (Read Only): USB is not a compound device. NoPowerSwitching: This bit should be written to support the external system port power switching implementation. 0 = Ports are power switched. 1 = Ports are always powered on. PowerSwitchingMode: This bit is only valid when NoPowerSwitching is cleared. This bit should be written 0. 0 = Global Switching; 1 = Individual Switching NumberDownstreamPorts (Read Only): USB supports two downstream ports.
23:13 12 11 10 9 8 7:0
Note: This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation.
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)
Bit Description HcRhDescriptorB Register (R/W) Reset Value = 00000000h
Offset 4Ch-4Fh 31:16
PortPowerControlMask: Global-power switching. This field is only valid if NoPowerSwitching is cleared and PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). 0 = Device not removable; 1 = Global-power mask. Port Bit relationship - Unimplemented ports are reserved, read/write 0. 0 = Reserved 1 = Port 1 2 = Port 2 ... 15 = Port 15
15:0
DeviceRemoveable: USB ports default to removable devices. 0 = Device not removable; 1 = Device removable. Port Bit relationship 0 = Reserved 1 = Port 1 2 = Port 2 ... 15 = Port 15 Unimplemented ports are reserved, read/write 0.
Note: This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation. Offset 50h-53h 31 30:18 17 16 15 HcRhStatus Register (R/W) Reset Value = 00000000h
ClearRemoteWakeupEnable (Write Only): Writing a 1 to this bit clears DeviceRemoteWakeupEnable. Writing a 1 has no effect. Reserved: Read/Write 0s. OverCurrentIndicatorChange: This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing a 0 has no effect. Read: LocalPowerStatusChange: Not supported. Always read 0. Write: SetGlobalPower: Write a 1 issues a SetGlobalPower command to the ports. Writing a 0 has no effect. Read: DeviceRemoteWakeupEnable: This bit enables ports' ConnectStatusChange as a remote wakeup event. 0 = Disabled; 1 = Enabled. Write = SetRemoteWakeupEnable: Writing a 1 sets DeviceRemoteWakeupEnable. Writing a 0 has no effect. Reserved: Read/Write 0s. OverCurrentIndicator: This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared. 0 = No over-current condition; 1 = Over-current condition. Read: LocalPowerStatus: Not Supported. Always read 0. Write: ClearGlobalPower: Writing a 1 issues a ClearGlobalPower command to the ports. Writing a 0 has no effect.
14:2 1 0
Note: This register is reset by the UsbReset state.
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)
Bit Description HcRhPortStatus[1] Register (R/W) Reset Value = 00000628h
Offset 54h-57h 31:21 20 19 18 17 16 Reserved: Read/Write 0s.
PortResetStatusChange: This bit indicates that the port reset signal has completed. 0 = Port reset is not complete; 1 = Port reset is complete. PortOverCurrentIndicatorChange: This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing a 0 has no effect. PortSuspendStatusChange: This bit indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed; 1 = Port resume is complete. PortEnableStatusChange: This bit indicates that the port has been disabled due to a hardware event (cleared PortEnableStatus). 0 = Port has not been disabled; 1 = PortEnableStatus has been cleared. ConnectStatusChange: This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit. Writing a 0 has no effect. 0 = No connect/disconnect event; 1 = Hardware detection of connect/disconnect event. If DeviceRemoveable is set, this bit resets to 1. Reserved: Read/Write 0s. Read: LowSpeedDeviceAttached: This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device; 1 = Low Speed device. Write: ClearPortPower: Writing a 1 clears PortPowerStatus. Writing a 0 has no effect. Read: PortPowerStatus: This bit reflects the power state of the port regardless of the power switching mode. 0 = Port power is off; 1 = Port power is on. Note: If NoPowerSwitching is set, this bit is always read as 1. Write: SetPortPower: Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.
15:10 9
8
7:5 4 3
Reserved: Read/Write 0s. Read: PortResetStatus: 0 = Port reset signal is not active; 1 = Port reset signal is active. Write: SetPortReset: Writing a 1 sets PortResetStatus. Writing a 0 has no effect. Read: PortOverCurrentIndicator: This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0 = No over-current condition; 1 = Overcurrent condition. Write: ClearPortSuspend: Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect. Read: PortSuspendStatus: 0 = Port is not suspended; 1 = Port is selectively suspended. Write: SetPortSuspend: Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect. Read: PortEnableStatus: 0 = Port disabled; 1 = Port enabled. Write: SetPortEnable: Writing a 1 sets PortEnableStatus. Writing a 0 has no effect. Read: CurrentConnectStatus: 0 = No device connected; 1 = Device connected. Note: If DeviceRemoveable is set (not removable) this bit is always 1. Write: ClearPortEnable: Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.
2 1 0
Note: This register is reset by the UsbReset state.
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)
Bit Description HcRhPortStatus[2] Register (R/W) Reset Value = 01000002h
Offset 58h-5Bh 31:21 20 19 18 17 16 Reserved: Read/Write 0s.
PortResetStatusChange: This bit indicates that the port reset signal has completed. 0 = Port reset is not complete; 1 = Port reset is complete. PortOverCurrentIndicatorChange: This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing a 0 has no effect. PortSuspendStatusChange: This bit indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed; 1 = Port resume is complete. PortEnableStatusChange: This bit indicates that the port has been disabled due to a hardware event (cleared PortEnableStatus). 0 = Port has not been disabled; 1 = PortEnableStatus has been cleared. ConnectStatusChange: This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit. Writing a 0 has no effect. 0 = No connect/disconnect event; 1 = Hardware detection of connect/disconnect event. If DeviceRemoveable is set, this bit resets to 1. Reserved: Read/Write 0s. Read: LowSpeedDeviceAttached: This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device; 1 = Low Speed device. Write: ClearPortPower: Writing a 1 clears PortPowerStatus. Writing a 0 has no effect. Read: PortPowerStatus: This bit reflects the power state of the port regardless of the power switching mode. 0 = Port power is off; 1 = Port power is on. Note: If NoPowerSwitching is set, this bit is always read as 1. Write: SetPortPower: Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.
15:10 9
8
7:5 4 3
Reserved: Read/Write 0s. Read: PortResetStatus: 0 = Port reset signal is not active; 1 = Port reset signal is active. Write: SetPortReset: Writing a 1 sets PortResetStatus. Writing a 0 has no effect. Read: PortOverCurrentIndicator: This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0 = No over-current condition; 1 = Overcurrent condition. Write: ClearPortSuspend: Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect. Read: PortSuspendStatus: 0 = Port is not suspended; 1 = Port is selectively suspended. Write: SetPortSuspend: Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect. Read: PortEnableStatus: 0 = Port disabled; 1 = Port enabled. Write: SetPortEnable: Writing a 1 sets PortEnableStatus. Writing a 0 has no effect. Read: CurrentConnectStatus: 0 = No device connected; 1 = Device connected. Note: If DeviceRemoveable is set (not removable) this bit is always 1. Write: ClearPortEnable: Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.
2 1 0
Note: This register is reset by the UsbReset state. Offset 5Ch-5Fh Offset 60h-9Fh Reserved Reserved Reset Value = 00000000h Reset Value = xxh
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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)
Bit Description HceControl Register (R/W) Reset Value = 00000000h
Offset 100h-103h 31:9 8 7 6 5 4 3 2 1 0 Reserved: Read/Write 0s.
A20State: Indicates current state of Gate A20 on keyboard controller. Compared against value written to 60h when GateA20Sequence is active. IRQ12Active: Indicates a positive transition on IRQ12 from keyboard controller occurred. Software writes this bit to 1 to clear it (set it to 0); a 0 write has no effect. IRQ1Active: Indicates a positive transition on IRQ1 from keyboard controller occurred. Software writes this bit to 1 to clear it (set it to 0); a 0 write has no effect. GateA20Sequence: Set by HC when a data value of D1h is written to I/O port 64h. Cleared by HC on write to I/O port 64h of any value other than D1h. ExternalIRQEn: When set to 1, IRQ1 and IRQ12 from the keyboard controller cause an emulation interrupt. The function controlled by this bit is independent of the setting of the EmulationEnable bit in this register. IRQEn: When set, the HC generates IRQ1 or IRQ12 as long as the OutputFull bit in HceStatus is set to 1. If the AuxOutputFull bit of HceStatus is 0, IRQ1 is generated: if 1, then an IRQ12 is generated. CharacterPending: When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus register is set to 0. EmulationInterrupt (Read Only): This bit is a static decode of the emulation interrupt condition. EmulationEnable: When set to 1 the HC is enabled for legacy emulation and will decode accesses to I/O registers 60h and 64h and generate IRQ1 and/or IRQ12 when appropriate. The HC also generates an emulation interrupt at appropriate times to invoke the emulation software.
Note: This register is used to enable and control the emulation hardware and report various status information. Offset 104h-107h 31:8 7:0 Reserved: Read/Write 0s. InputData: This register holds data written to I/O ports 60h and 64h. HceInput Register (R/W) Reset Value = 000000xxh
Note: This register is the emulation side of the legacy Input Buffer register. Offset 108h-10Bh 31:8 7:0 Reserved: Read/Write 0s. OutputData: This register hosts data that is returned when an I/O read of port 60h is performed by application software. HceOutput Register (R/W) Reset Value = 000000xxh
Note: This register is the emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software. Offset 10Ch-10Fh 31:8 7 6 5 4 3 2 1 0 Reserved: Read/Write 0s. Parity: Indicates parity error on keyboard/mouse data. Timeout: Used to indicate a time-out AuxOutputFull: IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and the IRQEn bit is set. Inhibit Switch: This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is NOT inhibited. CmdData: The HC will set this bit to 0 on an I/O write to port 60h and on an I/O write to port 64h the HC will set this bit to 1. Flag: Nominally used as a system flag by software to indicate a warm or cold boot. InputFull: Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write to address 60h or 64h. While this bit is set to 1 and emulation is enabled, an emulation interrupt condition exists. OutputFull: The HC will set this bit to 0 on a read of I/O port 60h. If IRQEn is set and AuxOutputFull is set to 0 then an IRQ1 is generated as long as this bit is set to 1. If IRQEn is set and AuxOutputFull is set to 1 then and IRQ12 will be generated a long as this bit is set to 1. While this bit is 0 and CharacterPending in HceControl is set to 1, an emulation interrupt condition exists. HceStatus Register (R/W) Reset Value = 00000000h
Note: This register is the emulation side of the legacy Status register.
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4.5 CS5530A ISA LEGACY I/O REGISTER SPACE
* Programmable Interval Timer Registers, see Table 4-29 * Programmable Interrupt Controller Registers, see Table 4-30 * Keyboard Controller Registers, see Table 4-31 * Real Time Clock Registers, see Table 4-32 * Miscellaneous Registers, see Table 4-33 (includes 4D0h and 4D1h Interrupt Edge/Level Select Registers and ACPI Timer Count Register at I/O Port 121Ch) The bit formats for the ISA Legacy I/O Registers plus two chipset-specific configuration registers used for interrupt mapping in the CS5530A are given in this section. These registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/output instructions (i.e., CPU direct R/W) with the designated I/O port address and 8-bit data. The registers are separated into the following categories: * DMA Channel Control Registers, see Table 4-27 * DMA Page Registers, see Table 4-28
Table 4-27. DMA Channel Control Registers
Bit Description DMA Channel 0 Address Register
I/O Port 000h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 001h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 002h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 003h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 004h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 005h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 006h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 007h (R/W) Written as two successive bytes, byte 0, 1. I/O Port 008h (R/W) Read 7 6 5 4 3 2 1 0 Write 7 6 5 4 3 2 1:0
DMA Channel 0 Transfer Count Register
DMA Channel 1 Address Register
DMA Channel 1 Transfer Count Register
DMA Channel 2 Address Register
DMA Channel 2 Transfer Count Register
DMA Channel 3 Address Register
DMA Channel 3 Transfer Count Register
DMA Status Register, Channels 3:0 Channel 3 Request: Request pending? 0 = No; 1 = Yes. Channel 2 Request: Request pending? 0 = No; 1 = Yes. Channel 1 Request: Request pending? 0 = No; 1 = Yes. Channel 0 Request: Request pending? 0 = No; 1 = Yes. Channel 3 Terminal Count: TC reached? 0 = No; 1 = Yes. Channel 2 Terminal Count: TC reached? 0 = No; 1 = Yes. Channel 1 Terminal Count: TC reached? 0 = No; 1 = Yes. Channel 0 Terminal Count: TC reached? 0 = No; 1 = Yes. DMA Command Register, Channels 3:0 DACK Sense: 0 = Active high; 1 = Active low. DREQ Sense: 0 = Active high; 1 = Active low. Write Selection: 0 = Late write; 1 = Extended write. Priority Mode: 0 = Fixed; 1 = Rotating. Timing Mode: 0 = Normal; 1 = Compressed. Channels 3 through 0: 0 = Disable; 1 = Enable. Reserved: Set to 0. 220 Revision 1.1
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Table 4-27. DMA Channel Control Registers (Continued)
Bit Description Software DMA Request Register, Channels 3:0
I/O Port 009h (WO) 7:3 2 1:0 Reserved: Set to 0. Reserved: Set to 0.
Channel Number Request Select: 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3. Note: Software DMA is not supported. DMA Channel Mask Register, Channels 3:0
I/O Port 00Ah (R/W) 7:3 2 1:0 Reserved: Set to 0.
Channel Mask: 0 = Not masked; 1 = Masked. Channel Number Mask Select: 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3. DMA Channel Mode Register, Channels 3:0
I/O Port 00Bh (WO) 7:6 5 4 3:2 1:0
Transfer Mode: 00 = Demand; 01 = Single; 10 = Block; 11 = Cascade. Address Direction: 0 = Increment; 1 = Decrement. Auto-initialize: 0 = Disable; 1 = Enable. Transfer Type: 00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved. Channel Number Mode Select: 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3. DMA Clear Byte Pointer Command, Channels 3:0 DMA Master Clear Command, Channels 3:0 DMA Clear Mask Register Command, Channels 3:0 DMA Write Mask Register Command, Channels 3:0 DMA Channel 4 Address Register
I/O Port 00Ch (WO) I/O Port 00Dh (WO) I/O Port 00Eh (WO) I/O Port 00Fh (WO) I/O Port 0C0h (R/W) Not used. I/O Port 0C2h (R/W) Not used. I/O Port 0C4h (R/W) Memory address bytes 1 and 0. I/O Port 0C6h (R/W) Transfer count bytes 1 and 0 I/O Port 0C8h (R/W) Memory address bytes 1 and 0. I/O Port 0CAh (R/W) Transfer count bytes 1 and 0. I/O Port 0CCh (R/W) Memory address bytes 1 and 0.
DMA Channel 4 Transfer Count Register
DMA Channel 5 Address Register
DMA Channel 5 Transfer Count Register
DMA Channel 6 Address Register
DMA Channel 6 Transfer Count Register
DMA Channel 7 Address Register
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Table 4-27. DMA Channel Control Registers (Continued)
Bit Description DMA Channel 7 Transfer Count Register
I/O Port 0CEh (R/W) Transfer count bytes 1 and 0. I/O Port 0D0h (R/W) Read 7 6 5 4 3 2 1 0 Write 7 6 5 4 3 2 1:0
DMA Status Register, Channels 7:4 Channel 7 Request: Request pending? 0 = No; 1 = Yes. Channel 6 Request: Request pending? 0 = No; 1 = Yes. Channel 5 Request: Request pending? 0 = No; 1 = Yes. Undefined Channel 7 Terminal Count: TC reached? 0 = No; 1 = Yes. Channel 6 Terminal Count: TC reached? 0 = No; 1 = Yes. Channel 5 Terminal Count: TC reached? 0 = No; 1 = Yes. Undefined DMA Command Register, Channels 7:4 DACK Sense: 0 = Active high; 1 = Active low. DREQ Sense: 0 = Active high; 1 = Active low. Write Selection: 0 = Late write; 1 = Extended write. Priority Mode: 0 = Fixed; 1 = Rotating. Timing Mode: 0 = Normal; 1 = Compressed. Channels 7 through 4: 0 = Disable; 1 = Enable. Reserved: Set to 0. Software DMA Request Register, Channels 7:4
I/O Port 0D2h (WO) 7:3 2 1:0 Reserved: Set to 0.
Request Type: 0 = Reset; 1 = Set. Channel Number Request Select: 00 = Illegal; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7. Note: Software DMA is not supported DMA Channel Mask Register, Channels 7:0
I/O Port 0D4h (R/W) 7:3 2 1:0 Reserved: Set to 0.
Channel Mask: 0 = Not masked; 1 = Masked. Channel Number Mask Select: 00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7. DMA Channel Mode Register, Channels 7:4
I/O Port 0D6h (WO) 7:6 5 4 3:2 1:0
Transfer Mode: 00 = Demand; 01 = Single; 10 = Block; 11 = Cascade. Address Direction: 0 = Increment; 1 = Decrement. Auto-initialize: 0 = Disabled; 1 = Enable. Transfer Type: 00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved. Channel Number Mode Select: 00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7. Channel 4 must be programmed in cascade mode. This mode is not the default. DMA Clear Byte Pointer Command, Channels 7:4 DMA Master Clear Command, Channels 7:4 DMA Clear Mask Register Command, Channels 7:4 DMA Write Mask Register Command, Channels 7:4
I/O Port 0D8h (WO) I/O Port 0DAh (WO) I/O Port 0DCh (WO) I/O Port 0DEh (WO)
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Table 4-28. DMA Page Registers
Bit Description DMA Channel 2 Low Page Register
I/O Port 081h (R/W) Address bits [23:16] (byte 2). I/O Port 082h (R/W) Address bits [23:16] (byte 2). I/O Port 083h (R/W) Address bits [23:16] (byte 2). I/O Port 087h (R/W) Address bits [23:16] (byte 2). I/O Port 089h (R/W) Address bits [23:16] (byte 2). I/O Port 08Ah (R/W) Address bits [23:16] (byte 2). I/O Port 08Bh (R/W) Address bits [23:16] (byte 2). I/O Port 08Fh (R/W) Refresh address. I/O Port 481h (R/W)
DMA Channel 3 Low Page Register
DMA Channel 1 Low Page Register
DMA Channel 0 Low Page Register
DMA Channel 6 Low Page Register
DMA Channel 7 Low Page Register
DMA Channel 5 Low Page Register
ISA Refresh Low Page Register
DMA Channel 2 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 081h. I/O Port 482h (R/W) DMA Channel 3 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 082h. I/O Port 483h (R/W) DMA Channel 1 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 083h. I/O Port 487h (R/W) DMA Channel 0 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 087h. I/O Port 489h (R/W) DMA Channel 6 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 089h. I/O Port 48Ah (R/W) DMA Channel 7 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 08Ah. I/O Port 48Bh (R/W) DMA Channel 5 High Page Register
Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 08Bh.
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Table 4-29. Programmable Interval Timer Registers
Bit Description
I/O Port 040h Write 7:0 Read 7 6 5:4 3:1 0 Counter Value PIT Timer 0 Status Counter Output: State of counter output signal. Counter Loaded: Last count written is loaded? 0 = Yes; 1 = No. Current Read/Write Mode: 00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, followed by MSB. Current Counter Mode: 0-5. BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). PIT Timer 0 Counter
I/O Port 041h Write 7:0 Read 7 6 5:4 3:1 0 Counter Value PIT Timer 1 Status (Refresh) Counter Output: State of counter output signal. Counter Loaded: Last count written is loaded? 0 = Yes; 1 = No. Current Read/Write Mode: 00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, followed by MSB. Current Counter Mode: 0-5. BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). PIT Timer 1 Counter (Refresh)
I/O Port 042h Write 7:0 Read 7 6 5:4 3:1 0 Counter Value PIT Timer 2 Status (Speaker) Counter Output: State of counter output signal. Counter Loaded: Last count written is loaded? 0 = Yes; 1 = No. Current Read/Write Mode: 00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, followed by MSB. Current Counter Mode: 0-5. BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal). PIT Mode Control Word Register PIT Timer 2 Counter (Speaker)
I/O Port 043h (R/W) 7:6 5:4 3:1 0
Counter Select: 00 = Counter 0; 01 = Counter 1; 10 = Counter 2; 11 = Read-back command (Note 1). Current Read/Write Mode: 00 = Counter latch command (Note 2); 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB, followed by MSB. Current Counter Mode: 0-5. BCD Mode: 0 = Binary; 1 = BCD (binary coded decimal).
Notes: 1. If bits [7:6] = 11: Register functions as Read Status Command Bit 5 = Latch Count, Bit 4 = Latch Status, Bit 3 = Select Counter 2, Bit 2 = Select Counter 1, Bit 1 = Select Counter 0, and Bit 0 = Reserved 2. If bits [5:4] = 00: Register functions as Counter Latch Command Bits [7:6] = Selects Counter, and [3:0] = Don't care
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Table 4-30. Programmable Interrupt Controller Registers
Bit Description Master / Slave PIC IWC1
I/O Port 020h / 0A0h (WO) 7:5 4 3 2 1 0 Reserved: Set to 0. Reserved: Set to 1. Trigger Mode: 0 = Edge; 1 = Level.
Vector Address Interval: 0 = 8-byte intervals; 1 = 4-byte intervals. Reserved: Set to 0 (cascade mode). Reserved: Set to 1 (ICW4 must be programmed). Master / Slave PIC ICW2 (after ICW1 is written)
I/O Port 021h / 0A1h (WO) 7:3 2:0
A[7:3]: Address lines [7:3] for base vector for interrupt controller. Reserved: Set to 0. Master / Slave PIC ICW3 (after ICW2 is written)
I/O Port 021h / 0A1h (WO) Master PIC ICW3 7:0 Cascade IRQ: Must be 04h.
Slave PIC ICW3 7:0 Slave ID: Must be 02h. Master / Slave PIC ICW4 (after ICW3 is written)
I/O Port 021h / 0A1h (WO) 7:5 4 3:2 1 0 Reserved: Set to 0.
Special Fully Nested Mode: 0 = Disable; 1 = Enable. This function is not implemented and should always be disabled (i.e., set this bit to 0). Reserved: Set to 0. Auto EOI: 0 = Normal EOI; 1 = Auto EOI. Reserved: Set to 1 (8086/8088 mode). Master / Slave PIC OCW1 (except immediately after ICW1 is written)
I/O Port 021h / 0A1h (R/W) 7 6 5 4 3 2 1 0
IRQ7 / IRQ15 Mask: 0 = Not Masked; 1 = Mask. IRQ6 / IRQ14 Mask: 0 = Not Masked; 1 = Mask. IRQ5 / IRQ13 Mask: 0 = Not Masked; 1 = Mask. IRQ4 / IRQ12 Mask: 0 = Not Masked; 1 = Mask. IRQ3 / IRQ11 Mask: 0 = Not Masked; 1 = Mask. IRQ2 / IRQ10 Mask: 0 = Not Masked; 1 = Mask. IRQ1 / IRQ9 Mask: 0 = Not Masked; 1 = Mask. IRQ0 / IRQ8 Mask: 0 = Not Masked; 1 = Mask. Master / Slave PIC OCW2 100 = Set rotate in Auto EOI mode 101 = Rotate on non-specific EOI command 110 = Set priority command (bits [2:0] must be valid) 111 = Rotate on specific EOI command (bits [2:0] must be valid)
I/O Port 020h / 0A0h (WO) 7:5 Rotate/EOI Codes
000 = Clear rotate in Auto EOI mode 001 = Non-specific EOI 010 = No operation 011 = Specific EOI (bits [2:0] must be valid) 4:3 2:0 Reserved: Set to 0. IRQ Number (000-111)
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Table 4-30. Programmable Interrupt Controller Registers (Continued)
Bit Description Master / Slave PIC OCW3
I/O Port 020h / 0A0h (WO) 7 6:5 Reserved: Set to 0. Special Mask Mode 00 = No operation 01 = No operation 4 3 2 1:0 Reserved: Set to 0. Reserved: Set to 1.
10 = Reset Special Mask Mode 11 = Set Special Mask Mode
Reserved: Set to 0. Poll Command at this address is not supported. Register Read Mode 00 = No operation 01 = No operation 10 = Read interrupt request register on next read of Port 20h 11 = Read interrupt service register on next read of Port 20h Master / Slave PIC Interrupt Request and Service Registers for OCW3 Commands
I/O Port 020h / 0A0h (RO) Interrupt Request Register 7 6 5 4 3 2 1 0
IRQ7 / IRQ15 Pending: 0 = Yes; 1 = No. IRQ6 / IRQ14 Pending: 0 = Yes; 1 = No. IRQ5 / IRQ13 Pending: 0 = Yes; 1 = No. IRQ4 / IRQ12 Pending: 0 = Yes; 1 = No. IRQ3 / IRQ11 Pending: 0 = Yes; 1 = No. IRQ2 / IRQ10 Pending: 0 = Yes; 1 = No. IRQ1 / IRQ9 Pending: 0 = Yes; 1 = No. IRQ0 / IRQ8 Pending: 0 = Yes; 1 = No.
Interrupt Service Register 7 6 5 4 3 2 1 0 IRQ7 / IRQ15 In-Service: 0 = No; 1 = Yes. IRQ6 / IRQ14 In-Service: 0 = No; 1 = Yes. IRQ5 / IRQ13 In-Service: 0 = No; 1 = Yes. IRQ4 / IRQ12 In-Service: 0 = No; 1 = Yes. IRQ3 / IRQ11 In-Service: 0 = No; 1 = Yes. IRQ2 / IRQ10 In-Service: 0 = No; 1 = Yes. IRQ1 / IRQ9 In-Service: 0 = No; 1 = Yes. IRQ0 / IRQ8 In-Service: 0 = No; 1 = Yes.
Note: The function of this register is set with bits [1:0] in a write to 020h.
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Table 4-31. Keyboard Controller Registers
Bit Description External Keyboard Controller Data Register
I/O Port 060h (R/W)
Keyboard Controller Data Register: All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 061h (R/W) 7 Port B Control Register Reset Value = 00x01100b
PERR#/SERR# Status (Read Only): Was a PCI bus error (PERR#/SERR#) asserted by a PCI device or by the CS5530A? 0 = No; 1 = Yes. This bit can only be set if ERR_EN (bit 2) is set 0. This bit is set 0 after a write to ERR_EN with a 1 or after reset. IOCHK# Status (Read Only): Is an I/O device reporting an error to the CS5530A? 0 = No; 1 = Yes. This bit can only be set if IOCHK_EN (bit 3) is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset. PIT OUT2 State (Read Only): This bit reflects the current status of the PIT Counter 2 (OUT2). Toggle (Read Only): This bit toggles on every falling edge of Counter 1 (OUT1). IOCHK Enable: 0 = Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control. 1 = Ignores the IOCHK# input signal and does not generate NMI.
6 5 4 3
2 1 0
PERR#/SERR# Enable: Generates an NMI if PERR#/SERR# is driven active to report an error. 0 = Enable; 1 = Disable PIT Counter2 (SPKR): 0 = Forces Counter 2 output (OUT2) to zero; 1 = Allows Counter 2 output (OUT2) to pass to the speaker. PIT Counter2 Enable: 0 = Sets GATE2 input low; 1 = Sets GATE2 input high. External Keyboard Controller Mailbox Register
I/O Port 062h (R/W)
Keyboard Controller Mailbox Register: Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]). I/O Port 064h (R/W) External Keyboard Controller Command Register
Keyboard Controller Command Register: All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# pin or cause a warm CPU reset. I/O Port 066h (R/W) External Keyboard Controller Mailbox Register
Keyboard Controller Mailbox Register: Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]). I/O Port 092h 7:2 1 0 Reserved: Set to 0. A20M# SMI Assertion: Assert A20M#. 0 = Enable mask; 1 = Disable mask. Fast CPU Reset: WM_RST SMI is asserted to the BIOS. 0 = Disable; 1 = Enable. This bit must be cleared before the generation of another reset. Port A Control Register (R/W) Reset Value = 02h
Table 4-32. Real-Time Clock Registers
Bit Description RTC Address Register
I/O Port 070h (WO) 7 6:0 NMI Mask: 0 = Enable; 1 = Mask.
RTC Register Index: A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
Note: This register is shadowed within the CS5530A and is read through the RTC Shadow Register (F0 Index BBh). I/O Port 071h (R/W) RTC Data Register
A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#. A write of this register sets the value into the register indexed by the RTC Address Register plus initiates a RTCCS#.
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Table 4-33. Miscellaneous Registers
Bit Description Secondary IDE Registers (R/W)
I/O Ports 170h-177h/376h
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to their configuration rather than generating standard ISA bus cycles. I/O Ports 1F0h-1F7h/3F6h Primary IDE Registers (R/W)
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to their configuration rather than generating standard ISA bus cycles. I/O Port 4D0h 7 6 5 4 3 2 1 0 Interrupt Edge/Level Select Register 1 (R/W) Reset Value = 00h
IRQ7 Edge or Level Select: Selects PIC IRQ7 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ6 Edge or Level Select: Selects PIC IRQ6 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ5 Edge or Level Select: Selects PIC IRQ5 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ4 Edge or Level Select: Selects PIC IRQ4 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ3 Edge or Level Select: Selects PIC IRQ3 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0. IRQ1 Edge or Level Select: Selects PIC IRQ1 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0.
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 4D1h 7 6 5 4 3 2 1 0 Interrupt Edge/Level Select Register 2 (R/W) Reset Value = 00h
IRQ15 Edge or Level Select: Selects PIC IRQ15 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ14 Edge or Level Select: Selects PIC IRQ14 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0. IRQ12 Edge or Level Select: Selects PIC IRQ12 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ11 Edge or Level Select: Selects PIC IRQ11 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ10 Edge or Level Select: Selects PIC IRQ10 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) IRQ9 Edge or Level Select: Selects PIC IRQ9 sensitivity configuration. 0 = Edge; 1 = Level. (Notes 1 and 2) Reserved: Set to 0.
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 121Ch-121Fh (Note) ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh
ACPI_COUNT (Read Only): This read-only register provides the current value for the ACPI timer. The timer counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported is at F0 Index 87h/F7h[0]. 31:24 23:0 Reserved: Always returns 0. Counter
Note: The ACPI Timer Count Register is also accessible through F1BAR+Offset 1Ch.
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4.6 V-ACPI I/O REGISTER SPACE
enables and as communication flags between BIOS and the ACPI OS. P_BLK is 32-bit aligned (one register block per processor) and contains two registers P_CNT and P_LVL2. P_LVL3 is currently not supported. -- P_CNT (Processor Control) - 16-bit register, Controls process duty cycle via CPU clock throttling. DUTY_WIDTH = 3 (can be widened) DUTY_OFFSET = 0 -- P_LVL2 (Enter C2 Power State) - 8-bit, read only register. When read, causes the processor to enter C2 power state. CMD_BLK contains one 8-bit register SMI_CMD which interprets and processes the ACPI commands (defined in Fixed ACPI Description Table, refer to ACPI Specification, Section 5.2.5). TST/SETUP_BLK is provided by the VSA technology code and contains two registers, SETUP_IDX and SETUP_DATA for the purpose of configuring the CS5530A. Specifically, this pair of registers enables system software to map GPIO pins on the CS5530A to PM1A_STS and GPE0_STS register bits. GPE0_BLK has registers used to enable system software to configure GPIO (General Purpose I/O) pins to generate SCI interrupts. GPE0_BLK is a 32-bit block aligned on a 4byte boundary. It contains two 16-bit registers, GPE0_STS and GPE0_EN, each of which must be configured by the BIOS POST. In order for a GPE0_STS bit to generate an SCI, the corresponding enable bit in GPE0_EN must be set. Table 4-34 gives the bit formats of the V-ACPI I/O registers. The register space designated as V-ACPI I/O does not physically exist in the CS5530A. ACPI is supported in the CS5530A by virtualizing this register space, called V-ACPI. In order for ACPI to be supported, the V-ACPI VSA module must be included in the BIOS. The register descriptions that follow, are supplied here for reference only. Fixed Feature Space registers are required to be implemented by all ACPI-compatible hardware. The Fixed Feature registers in the VSA/ACPI solution are mapped to normal I/O space starting at offset AC00h; however, the designer can relocate this register space at compile time, hence are hereafter referred to as ACPI_BASE. Registers within V-ACPI (Virtualized ACPI) I/O space must only be accessed on their defined boundaries. For example, byte aligned registers must not be accessed via WORD I/O instructions, WORD aligned registers must not be accessed as DWORD I/O instructions, etc. The V-ACPI I/O Register Space can be broken up into major blocks: * PM Event Block 1A (PM1A_EVT_BLK) * PM Event Block 1A Control (PM1A_CNT_BLK) * Processor Register Block (P_BLK) * Command Block (CMD_BLK) * Test/Setup Block (TST/SETUP_BLK) * General Purpose Enable 0 Block (GPE0_BLK) PM1A_EVT_BLK is 32-bit aligned and contains two 16-bit registers, PM1A_STS and PM1A _EN. PM1A_CNT_BLK is 32-bit aligned and contains one 16-bit register, PM1A_CNT. PM1A_CNT contains the Fixed Feature control bits used for various power management
Table 4-34. V-ACPI Registers
Bit Description P_CNT -- Processor Control Register (R/W) Reset Value = 00000000h
ACPI_BASE 00h-03h 31:5 4 3 2:0 Reserved: Always 0.
THT_EN: Enables throttling of the clock based on the CLK_VAL field. Reserved: Always 0. CLK_VAL: Clock throttling value. CPU duty cycle = 000 = Reserved 001 = 12.5% 010 = 25% 011 = 37.5% 100 = 50% 101 = 62.5% 110 = 75% 111 = 87.5% Reset Value = 00h
ACPI_BASE 04h
P_LVL2 -- Enter C2 Power State Register (RO)
Reading this 8-bit read only register causes the processor to enter the C2 power state. Reads of P_LVL2 return 0. Writes have no effect. ACPI_BASE 05h ACPI_BASE 06h Reserved SMI_CMD -- OS/BIOS Requests Register (R/W) Reset Value = 00h Reset Value = 00h
Interpret and process the ACPI commands (defined in Fixed ACPI Description Table, refer to ACPI Specification, Section 5.2.5). 0x01 - ACPI_ENABLE 0x02 - ACPI_DISABLE 0x03 - S4BIOS_REQ (optional) ACPI_BASE 07h Reserved Reset Value = 00h
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Table 4-34. V-ACPI Registers (Continued)
Bit Description PM1A_STS -- PM1A Status Register (R/W) Reset Value = 0000h
ACPI_BASE 08h-09h 15 14:11 10 9
WAKE_STS: Wake Status - Set when system was in sleep state and an enabled wakeup occurs. Reserved RTC_STS: Real Time Clock Status - This bit changes to 1 if an RTC alarm causes a wake up event. This bit is only set upon wakeup from a sleep state and IRQ8 is asserted by the RTC. Refer to Table 4-37. SLPBTN_STS: Sleep Button Status (Optional) - This bit changes to 1 when the sleep button is pressed. If SLPBTN_EN is set, an SCI interrupt is generated. This bit must be configured to be set by a GPIO pin using SETUP_IDX values 0x10-0x17 in order to be set. Refer to Table 4-36.
8
PWRBTN_STS: Power Button Status - This bit is set when power button is pressed. If PWRBTN_EN is set, an SCI interrupt is asserted. This bit must be configured to be set by a GPIO pin using SETUP_IDX values 0x10-0x17 in order to be set. Refer to Table 4-36.
7:6 5 4 3:1 0
Reserved GBL_STS: Global Status - The BIOS sets GBL_STS to 1 to release its global lock and return control to the ACPI OS. At the same time GBL_STS is set, the BIOS generates an SCI. BM_STS: Bus Master Status - This bit is not supported by V-ACPI. Reserved TMR_STS: ACPI Timer Status - This bit changes to 1 whenever bit 23 of the ACPI timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch) changes state. The ACPI OS is responsible for clearing TMR_STS. If TMR_EN (ACPI_BASE 0Ah[0] is also set, then a SCI interrupt is asserted.
Note: Status bits are "sticky". A write of a one (1) to a given bit location will reset the bit. ACPI_BASE 0Ah-0Bh 15:11 10 9 8 7:6 5 4:1 0 Reserved RTC_EN: Real Time Clock Enable - If set, an SCI is asserted when RTC_STS changes to 1. SLPBTN_EN: Sleep Button Enable (Optional) - If set, an SCI is asserted when SLPBTN_STS changes to 1. PWRBTN_EN: Power Button Enable - If set, an SCI is asserted when PWRBTN_STS changes to 1. Reserved GBL_EN: Global Lock Enable - If set, writing a 1 to GBL_STS causes an SCI to be asserted. Reserved TMR_EN: ACPI Timer Enable - If set, an SCI is asserted when bit 23 of the ACPI timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch) changes state. PM1A_CNT -- PM1A Control Register (R/W) Reset Value = 0000h PM1A_EN -- PM1A Enable Register (R/W) Reset Value = 0000h
ACPI_BASE 0Ch-0Dh 15:14 13 12:10 Reserved
SLP_EN (WO): Sleep Enable (Write Only) - Setting this bit causes the system to enter the sleep state defined by SLP_TYPx. Reads of this bit always return zero. SLP_TYPx: Sleep Type - Defines the type of sleep state the system enters when SLP_EN (bit 13) is set. 000 = Sleep State S0 (Full on) 001 = Sleep State S1 010 = Sleep State S2 011 = Reserved 100 = Sleep State S4 101 = Sleep State S5 (Soft off) 110 = Reserved 111 = Reserved
9:3 2
Reserved GBL_RLS (WO): Global Lock Release (Write Only) - Used by ACPI OS to raise an event to the BIOS software (SMI). Used by ACPI driver to indicate a release of the global lock and the setting of the pending bit in the FACS table (refer to ACPI Specification, Section 5.2.8). BM_RLD: This bit is not supported by V-ACPI. SCI_EN: System Controller Interrupt Enable - Selects whether power management events are SCI or SMI. Set by hardware based on an ACPI_ENABLE/ACPI_DISABLE written to the SMI_CMD port. SETUP_IDX -- Setup Index Register (R/W) Reset Value = 0000h
1 0
ACPI_BASE 0Eh-0Fh
SETUP_IDX is a 16-bit register that references an internal setting in the VSA (refer to Table 4-35). A read of SETUP_IDX returns the last value written to SETUP_IDX. A write of SETUP_IDX selects the index for a corresponding write to SETUP_DATA. Writes of any undefined index values to SETUP_IDX are ignored. If the current value of SETUP_IDX is invalid, a read of SETUP_DATA returns 0.
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Table 4-34. V-ACPI Registers (Continued)
Bit Description GPE0_STS -- General Purpose Event 0 Status Register (R/W) Reset Value = 0000h
ACPI_BASE 10h-11h
Each bit is set by an external event and cleared by a write of a one to that bit. The GPE0_STS bits are mapped to specific, chipset-resident GPIO signals using the SETUP_IDX and SETUP_DATA registers. Refer to Tables 4-35 through 4-37. 15 14 13 12 11 10 9 8 7 6 OEM_GPE_S15: Original Equipment Manufacturer General Purpose Event Status Bit 15 - OEM defined. OEM_GPE_S14: Original Equipment Manufacturer General Purpose Event Status Bit 14 - OEM defined. OEM_GPE_S13: Original Equipment Manufacturer General Purpose Event Status Bit 13 - OEM defined. OEM_GPE_S12: Original Equipment Manufacturer General Purpose Event Status Bit 12 - OEM defined. OEM_GPE_S11: Original Equipment Manufacturer General Purpose Event Status Bit 11 - OEM defined. OEM_GPE_S10: Original Equipment Manufacturer General Purpose Event Status Bit 10 - OEM defined. OEM_GPE_S09: Original Equipment Manufacturer General Purpose Event Status Bit 9 - OEM defined. OEM_GPE_S08: Original Equipment Manufacturer General Purpose Event Status Bit 8 - OEM defined. OEM_GPE_S07: Original Equipment Manufacturer General Purpose Event Status Bit 7 - OEM defined. OEM_GPE_S06: Original Equipment Manufacturer General Purpose Event Status Bit 6 - OEM defined. The recommended mapping for the lid switch input is to use GPIO6. If the recommended mapping is used, this bit (bit 6) needs to be mapped to GPIO6 at boot time via SETUP_IDX and SETUP_DATA. Similarly, the lid switch input needs to be routed to GPIO6 in hardware. If this method is selected, this bit is defined as: LID_STS: Lid Status - Set when lid state changes. If LID_EN (ACPI_BASE 12h[6] is set, a SCI interrupt is asserted. Reset by writing a 1 to this bit. 5 4 3 2 1 0 OEM_GPE_S05: Original Equipment Manufacturer General Purpose Event Status Bit 5 - OEM defined. OEM_GPE_S04: Original Equipment Manufacturer General Purpose Event Status Bit 4 - OEM defined. OEM_GPE_S03: Original Equipment Manufacturer General Purpose Event Status Bit 3 - OEM defined. OEM_GPE_S02: Original Equipment Manufacturer General Purpose Event Status Bit 2 - OEM defined. OEM_GPE_S01: Original Equipment Manufacturer General Purpose Event Status Bit 1 - OEM defined. OEM_GPE_S00: Original Equipment Manufacturer General Purpose Event Status Bit 0 - OEM defined. GPE0_EN -- General Purpose Event 0 Enable Register (R/W) Reset Value = 0000h
ACPI_BASE 12h-13h 15 14 13 12 11 10 9 8 7 6 5 4 3 2
OEM_GPE_E15: Original Equipment Manufacturer General Purpose Event Enable Bit 15 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E14: Original Equipment Manufacturer General Purpose Event Enable Bit 14 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E13: Original Equipment Manufacturer General Purpose Event Enable Bit 13 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E12: Original Equipment Manufacturer General Purpose Event Enable Bit 12 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E11: Original Equipment Manufacturer General Purpose Event Enable Bit 11 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E10: Original Equipment Manufacturer General Purpose Event Enable Bit 10 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E09: Original Equipment Manufacturer General Purpose Event Enable Bit 9 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E08: Original Equipment Manufacturer General Purpose Event Enable Bit 8 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E07: Original Equipment Manufacturer General Purpose Event Enable Bit 7 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. LID_EN: Lid Enable - Enables LID_STS to generate a SCI when set. OEM_GPE_E05: Original Equipment Manufacturer General Purpose Event Enable Bit 5 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E04: Original Equipment Manufacturer General Purpose Event Enable Bit 4 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E03: Original Equipment Manufacturer General Purpose Event Enable Bit 3 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E02: Original Equipment Manufacturer General Purpose Event Enable Bit 2 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set.
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Table 4-34. V-ACPI Registers (Continued)
Bit 1 0 Description OEM_GPE_E01: Original Equipment Manufacturer General Purpose Event Enable Bit 1 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. OEM_GPE_E00: Original Equipment Manufacturer General Purpose Event Enable Bit 0 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. SETUP_DATA -- Setup Data Register (R/W) Reset Value = 00000000h
ACPI_BASE 14h-17h
During a read operation, SETUP_DATA returns the value of the internal setting specified by the current value in SETUP_IDX (ACPI_ABASE 0Eh-0Fh) ACPI_BASE 18h-1Fh Reserved for future V-ACPI Implementations. Reserved Reset Value = 00h
Table 4-35. SETUP_IDX Values
Index 0x00 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x50 0x60 0x61 0x62 0x63 0x64 Operation No operation Configure GPIO0 to PM1A_STS or GPE0_STS bits Configure GPIO1 to PM1A_STS or GPE0_STS bits Configure GPIO2 to PM1A_STS or GPE0_STS bits Configure GPIO3 to PM1A_STS or GPE0_STS bits Configure GPIO4 to PM1A_STS or GPE0_STS bits Configure GPIO5 to PM1A_STS or GPE0_STS bits Configure GPIO6 to PM1A_STS or GPE0_STS bits Configure GPIO7 to PM1A_STS or GPE0_STS bits Configure IRQ0 to wakeup system Configure IRQ1 to wakeup system Do not use - Reserved for cascade interrupt Configure IRQ3 to wakeup system Configure IRQ4 to wakeup system Configure IRQ5 to wakeup system Configure IRQ6 to wakeup system Configure IRQ7 to wakeup system Configure IRQ8 to wakeup system (Defaults to RTC_STS in PM1A_STS) Configure IRQ9 to wakeup system. Configure IRQ10 to wakeup system. Configure IRQ11 to wakeup system Configure IRQ12 to wakeup system Do not use - Reserved for math coprocessor Configure IRQ14 to wakeup system Configure IRQ15 to wakeup system Generate GBL_STS - Sets the GLB_STS bit and generates a SCI to the OS Configure IRQ to be used for SCI Enable reads of ACPI registers Do atomic I/O sequence Video power Soft SMI AX = 6000 emulation Soft SMI AX = 6001 emulation Soft SMI AX = 6002 emulation Soft SMI AX = 6003 emulation Audio power control
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Table 4-36. GPIO Mapping (0x10-0x17)
SETUP_ DATA xx Value 0x00 0x08 0x09 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F No mapping - Do not use this GPIO pin Assign GPIOx to PWRBTN_STS bit in PM1A_STS Assign GPIOx to SLPBTN_STS in PM1A_STS Assign GPIOx to bit 0 in GPE0_STS register Assign GPIOx to bit 1 in GPE0_STS register Assign GPIOx to bit 2 in GPE0_STS register Assign GPIOx to bit 3 in GPE0_STS register Assign GPIOx to bit 4 in GPE0_STS register Assign GPIOx to bit 5 in GPE0_STS register Assign GPIOx to bit 6 in GPE0_STS register Assign GPIOx to bit 7 in GPE0_STS register Assign GPIOx to bit 8 in GPE0_STS register Assign GPIOx to bit 9 in GPE0_STS register Assign GPIOx to bit 10 in GPE0_STS register Assign GPIOx to bit 11 in GPE0_STS register Assign GPIOx to bit 12 in GPE0_STS register Assign GPIOx to bit 13 in GPE0_STS register Assign GPIOx to bit 14 in GPE0_STS register Assign GPIOx to bit 15 in GPE0_STS register Function
y Value (y values may be ORed together to get the desired combination of features) 0x01 0x02 0x04 0x08 Falling edge Rising edge Power button Reserved
Note: For GPIO mapping, a value of 0000zyxx is used where: z = a runtime/wake indicator y = the edge to be used xx = a bit in either PM1A_STS or GPE0_STS When using V-ACPI both edges of GPIO6 can be sensed. When using the CS5530A, GPIO6 provides additional hardware that enables the chipset to generate an SMI on both the rising and falling edges of the input signal.
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Table 4-37. IRQ Wakeup Status Mapping (0x30-0x3F)
SETUP_ DATA 0 0x0a 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Function Do not wakeup on IRQ activity. Assign IRQ Wake to bit 10 in PM1A_STS register Assign IRQ Wake to bit 0 in GPE0_STS register Assign IRQ Wake to bit 1 in GPE0_STS register Assign IRQ Wake to bit 2 in GPE0_STS register Assign IRQ Wake to bit 3 in GPE0_STS register Assign IRQ Wake to bit 4 in GPE0_STS register Assign IRQ Wake to bit 5 in GPE0_STS register Assign IRQ Wake to bit 6 in GPE0_STS register Assign IRQ Wake to bit 7 in GPE0_STS register Assign IRQ Wake to bit 8 in GPE0_STS register Assign IRQ Wake to bit 9 in GPE0_STS register Assign IRQ Wake to bit 10 in GPE0_STS register Assign IRQ Wake to bit 11 in GPE0_STS register Assign IRQ Wake to bit 12 in GPE0_STS register Assign IRQ Wake to bit 13 in GPE0_STS register Assign IRQ Wake to bit 14 in GPE0_STS register Assign IRQ Wake to bit 15 in GPE0_STS register
Note: When the ability to wakeup on an IRQ is desired use Index 0x31 through 0x3F. This will allow sensing of interrupts while sleeping and waking of the system when activity occurs. The desired GPE0 Status bit will only be set if the system is sleeping and a wake event occurs. The system will only wake if the status bit is enabled in the corresponding enable register. IRQ8 (RTC) is assigned to the RTC_STS bit in the PM1A_STS register by default and should NOT be changed. For enabling and selection of the GPE0 Status bit to be set when Wake on IRQ Activity is desired, use the SETUP_DATA values listed above.
Table 4-38. Commands (0x41-0x43, and 0x50)
Index 0x41 Function Configure IRQ to be used for SCI: When mapping the SCI interrupt SETUP_IDX contains the number of the IRQ to be used for the SCI. Valid values are 3-7, 9-12, and 14-15. Invalid values will not change the assignment of the SCI IRQ. The default value for the SCI IRQ is 9. Enable Reads of ACPI Registers: Prior to the issuance of this command only WRITES can be performed to the V-ACPI Fixed feature registers. This command MUST be issued to enable reading of the registers. This is to prevent the User Def 1 hook on NON-ACPI systems from interfering with system functions. Do Atomic I/O Sequence: This command allows a sequence of I/O operations to be done with no interruption. Certain SuperI/O chips must receive unlock codes with NO intervening I/O. In addition other SuperI/O chips do not allow I/O to devices while in configuration mode. This command will insure that I/O operations are completed without interruption. The address of a sequence of I/O commands is placed in the SETUP_DATA register. The command sequence will then be processed immediately. The I/O command sequence consists of two parts: the signature/length block and the I/O block. There is only one signature/length block. There may be one or more I/O blocks. The signature block consists of four DWORDs (see Table 4-39). The I/O block consists of four bytes followed by three DWORDs (see Table 4-40). 0x50 Video Power: This command will control the power to the SoftVGA. If SETUP_DATA is written with a 0, power will be turned off. If a 1 is written, power will be turned on.
0x42
0x43
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Table 4-39. Signature/Length Block for 0x43
Byte Offset 0 4 8 12 Value Signature: Always 0x00000070 Length: The length of the entire buffer including the signature block in bytes. Reserved: Set to 0 Reserved: Set to 0
Table 4-40. I/O Block for 0x43
Byte Offset 0 Description BYTE: Operation Type. 1 = Read 2 = Write 3 = Read/And/Or/Write 4 = Define index and data ports In addition, values may be OR'ed in to the upper two bits of this byte to indicate that special functions are desired. 0x80 = Do not perform this operation (convert to NO-OP). 0x40 = This is an index operation. 1 2 BYTE: Reserved set to 0 BYTE: I/O Length - Determines whether a BYTE, WORD or DWORD operation is performed. 1 = BYTE operation 2 = WORD operation 3 = DWORD operation If BYTE 0 is a 4, then this field is used to indicate the size of the index write. 3 4 BYTE: Reserved set to 0 DWORD: I/O Address - This is the address in the I/O space to be used. It is always a WORD value. If this is a define index/data port operation, this DWORD contains the I/O address of the index port. If this is an index operation, other than define, this DWORD contains the value to be written to the index port. 8 DWORD: I/O Data - The meaning depends on the operation type. Read = This is where the data read from the I/O port will be placed. Write = This is the data to write to the I/O port. Read/AND/OR/Write = This is the data that will be ANDed with the data read from the I/O port. Define index/data port - This DWORD contains the I/O address of the data port. 12 DWORD: OR Data - This field is only used in a Read/AND/OR/Write operation. It contains the data that will be OR'ed after the data read was AND'ed with the previous field. After the OR is done, the data will be re-written to the I/O port.
Note: In all cases if the data called for is shorter than the field, the data will be stored or retrieved from the least significant portion of the DWORD.
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Table 4-41. Audio Soft SMI Emulation (0x60-0x63)
Soft SMI AX 0x6000 0x6001 0x6002 0x6003 SETUP_IDX 0x60 0x61 0x62 0x63 SETUP_DATA BP register value BP register value BX register value BX register value
Note: Arbitrary registers cannot be set in ASL code before issuing a soft SMI. These commands provide an I/O interface to allow AUDIO Soft SMIs to be emulated.
Table 4-42. Audio Power Control (0x64)
Data Value 0 1 2 3 Action Power codec off and mute output Power codec off, do not mute (allows CD to play) Power codec on and un-mute output Power codec on only
Note: This command allows control of power to the audio codec as well as control of amplifier muting.
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5.0
Electrical Specifications
5.1.2 Unused Input Pins All inputs not used by the system designer and not listed in Table 5-1 should be kept at either VSS or VDD. To prevent possible spurious operation, connect active-high inputs to ground through a 20-kohm (10%) pull-down resistor and active-low inputs to VDD through a 20-kohm (10%) pull-up resistor. 5.1.3 NC-Designated Pins Pins designated NC should be left disconnected. Connecting an NC pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 5.1.4 Power/Ground Connections and Decoupling Testing and operating the CS5530A requires the use of standard high frequency techniques to reduce parasitic effects. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low-impedance wiring, and by using all of the VDD and VSS pins.
This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, and DC/AC characteristics for the Geode CS5530A. All voltage values in the electrical specifications are with respect to VSS unless otherwise noted. For detailed information on the PCI bus electrical specification refer to Chapter 4 of the PCI Bus Specification, Revision 2.1.
5.1
ELECTRICAL CONNECTIONS
5.1.1 Pull-Up Resistors Table 5-1 lists the pins that are internally connected to a 20-kohm pull-up resistor. When unused, these inputs do not require connection to an external pull-up resistor.
Table 5-1. Pins with Weak Internal Pull-Up
Signal Name IOR# IOW# MEMR# MEMW# SBHE# SA[19:0]/ SD[19:0] Type I/O I/O I/O I/O I/O I/O Pin No. AE12 AC11 AE19 AF20 AE17 AD10, AE11, AF12, AD11, AE25, AD24, AD22, AE21, AF21, AC20, AD19, AF19, AF4, AF5, AD5, AF6, AC6, AD9, AE6, AD9
5.2
ABSOLUTE MAXIMUM RATINGS
Table 5-2 lists absolute maximum ratings for the CS5530A. Stresses beyond the listed ratings may cause permanent damage to the device. Exposure to conditions beyond these limits may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings may also result in reduced useful life and reliability These are stress ratings only and do not imply that operation under any conditions other than those listed under Table 5-3 is possible.
5.3
OPERATING CONDITIONS
Table 5-3 lists the recommended operating conditions for the CS5530A.
Table 5-2. Absolute Maximum Ratings
Parameter Operating Case Temperature Storage Temperature Supply Voltage Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK -0.5 -0.5 Min 0 -65 Max 110 150 4.0 5.5 10 25 Units C C V V mA mA Power Applied Power Applied Comments Power Applied No Bias
Table 5-3. Operating Conditions
Symbol TC VDD 1. Parameter (Note 1) Operating Case Temperature Supply Voltage Min 0 3.14 Max 85 3.46 Units C V Comments
For video interface specific parameters, refer to Table 5-17 "CRT, TFT/TV and MPEG Display Timing" on page 250.
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5.4 DC CHARACTERISTICS
All DC parameters and current measurements in this section were measured under the operating conditions listed in Table 5-3 on page 237, unless otherwise noted.
Table 5-4. DC Characteristics
Symbol VIL Parameter Low Level Input Voltage (Note 1) 8 mA CLK IDE PCI VIH High Level Input Voltage (Note 1) 8 mA CLK IDE PCI VOL 2.0 2.0 2.0 0.5VDD VDD+0.5 V VDD = 3.14V -0.5 0.8 0.8 0.8 0.3VDD V VDD = 3.14V Min Typ Max Units Comments
Low Level Output Voltage (Note 1) 8 mA DOTCLK FP_CLK IDE PCI USB 0.4 0.4 0.4 0.5 0.1VDD 0.3 V VDD = 3.14V, IOL = 8 mA VDD = 3.14V, IOL = 20 mA VDD = 3.14V, IOL = 12 mA VDD = 3.14V, IOL = 12 mA VDD = 3.14V, IOL = 1.5 mA RL = 1.5 K to VDD, VDD = 3.46V
VOH
High Level Output Voltage (Note 1) 8 mA DOTCLK FP_CLK IDE PCI USB 2.4 2.4 2.4 2.4 0.9VDD 2.8 VDD V VDD = 3.14V, IOH = -8 mA VDD = 3.14V, IOH = -20 mA VDD = 3.14V, IOH = -12 mA VDD = 3.14V, IOH = -400 A VDD = 3.14V, IOH = -0.5 mA VDD = 3.14V, RL = 15 K to VSS
ILEAK
Input Leakage Current Including Hi-Z Output Leakage (Note 1) 8 mA, CLK, DOTCLK, FP_CLK, IDE, PCI +/-10 +/-200 A VDD = VDDIO = 3.46V, VPAD = 0 to 3.46V, Note 2 VDD = VDDIO = 3.46V, VPAD = 3.46 to 5.5V, Note 2
IPU
Weak Pull-Up Current (Note 1) 8 mA -50 A VDDIO = 3.46V, Note 2
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Table 5-4. DC Characteristics (Continued)
Symbol IOH Parameter Output High Current (Note 1) 8 mA FP_CLK IDE PCI IOL Output Low Current (Note 1) 8 mA FP_CLK IDE PCI VH VDI VCM VSE VCRS Hysteresis Voltage 8 mA, CLK (Note 1) USB - Differential Input Sensitivity USB - Differential Common Mode Range USB - Single Ended Receiver Threshold 1.5 350 0.2 0.8 0.8 2.5 2.0 mV V V V 8 12 12 VDD = VDDIO = VDDmin = 3.14V VDD = VDDIO = VDDmin = 3.14V VT+ - VT|(D+)-(D-)|, within VCM, Note 3 Includes VDI range mA VDD = VDDIO = VDDmin = 3.14V -0.5 -8 -12 -0.5 VDD = VDDIO = VDDmin= 3.14V mA VDD = VDDIO = VDDmin = 3.14V Min Typ Max Units Comments
USB - Output Signal Crossover Voltage Low Speed Full Speed 1.3 1.3 2.0 2.0 V V VDD = 3.14V to 3.46V, See Figure 5-9 and Figure 5-10 on page 248
CIN
Input Capacitance (Note 1) 8 mA CLK IDE PCI 5 5 12 25 10 7 pF Note 3 pF Note 3
COUT 1. 2. 3.
Output Capacitance - All Digital Drivers
Pins with this buffer type are listed in Table 2-3 "352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name" on page 19. Pins with a pull-up always enabled are denoted in Table 5-1 "Pins with Weak Internal Pull-Up" on page 237. Note that the leakage specification does not apply to hard-wired pull-ups. Not 100% tested.
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5.4.1 Definition of System Conditions for Measuring "On" Parameters The current of the CS5530A is highly dependent on the lute maximum CS5530A current parameters. Table 5-6 proDCLK (DOT clock). Table 5-5 shows how these factors are vides the CS5530A's core, DAC, and PLL DC controlled when measuring the typical average and absocharacteristics during various power states.
Table 5-5. System Conditions Used to Determine CS5530A's Current Used During the "On" State
System Conditions CPU Current Measurement Typical Average Absolute Maximum 1. 2. 3. 4. VDD (Note 1) Nominal Max DCLK Frequency (Note 2) 50 MHz (Note 3) 135 MHz (Note 4)
See Table 5-3 on page 237 for nominal and maximum voltages. Not all system designs support display modes that require a DCLK of 157 MHz. Therefore, absolute maximum current will not be realized in all system designs. A DCLK frequency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz, using a display image of vertical stripes (4-pixel wide) alternating between black and white with power management disabled. A DCLK frequency of 157 MHz is derived by setting the display mode to 1280x1024x8 bpp at 85 Hz, using a display image of vertical stripes (1-pixel wide) alternating between black and white with power management disabled.
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Table 5-6. DC Characteristics During Power States
Symbol Core (Note 1) IDD_CORE IDDAI_CORE IDDSM_CORE IDDSS_CORE DAC (Note 1) IDD_DAC IDDAI_DAC IDDSM_DAC IDDSS_DAC PLL (Note 1) IDD_PLL IDDAI_PLL IDDSM_PLL IDDSS_PLL EXTVREFIN IDD_EXTVREFIN 1. 2. 3. 4. 5. 6. Active IDD 75 A Active IDD Active Idle IDD Suspend Mode IDD Standby IDD 6 6 0.3 0.2 6 mA mA mA mA Note 4 Note 5 Note 6 Active IDD Active Idle IDD Suspend Mode IDD Standby IDD 60 60 0.2 0.2 85 mA mA mA mA Note 2 and Note 3 Note 4 Note 5 Note 6 Active IDD Active Idle IDD Suspend Mode IDD Standby IDD 145 85 29 5.7 255 mA mA mA mA Note 2 and Note 3 Note 4 Note 5 Note 6 Parameter Min Typ Max Units Comments
Outputs unloaded. Maximum current is measured under the following assumptions: PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 157 MHz, and VID_CLK = 133 MHz. Typical current is measured under the following assumptions: PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 50 MHz, and VID_CLK = 0 MHz. Active Idle current is measured under the following assumptions with SUSPA# asserted: PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 50 MHz, and VID_CLK = 0 MHz. Suspend current is measured under the following assumptions with SUSPA# asserted: PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 0 MHz, and VID_CLK = 0 MHz. Standby current is measured under the following assumptions with SUSPA# and SUSP_3V (stop clock signal) asserted: PCICLK = 0 MHz, USBCLK = 0 MHz, DCLK = 0 MHz, and VID_CLK = 0 MHz.
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5.5 AC CHARACTERISTICS
The following tables list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. The rising-clock-edge reference level, VREF, and other reference levels are shown in Table 5-7. Input or output signals must cross these levels during testing. Input setup and hold times are specified minimums that define the smallest acceptable sampling window for which a synchronous input signal must be stable for correct operation.
Table 5-7. Drive Level and Measurement Points for AC Characteristics
Symbol VREF VDD VSS Voltage (V) 1.5 3.14 0
Table 5-8. AC Characteristics
Symbol tSU tH tLH Parameter Input Setup Time to PCICLK Input Hold Time to PCICLK Min 7 0 Typ Max Unit ns ns Comments (Note 1) See Figures 5-1 and 5-2 on page 243
Low to High Propagation Delay (Referenced to PCICLK, Note 2) PCI 2 11 ns See Figure 5-2 on page 243 and Figure 5-3 on page 244 (also known as tVAL)
tHL
High to Low Propagation Delay (Referenced to PCICLK, Note 2) PCI 2 11 ns See Figure 5-2 on page 243 and Figure 5-4 on page 244 (also known as tVAL)
tRISE/FALL
Rising/Falling Edge Rate IDE 1.25 V/ns See Figures 5-1 and 5-2 on page 243, Note 3
1. 2. 3.
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF. Pins with this buffer type are listed in Table 2-3 "352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name" on page 19. Not 100% tested.
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90% 10%
90% 10%
tRISE
tFALL
CLK
VDD VSS tLH/tHL Max tLH/tHL Min
VREF = 50% VDD
OUTPUTS
Valid Output n
Valid Output n+1 tSU Min tH Min
VREF = 50% VDD
INPUTS
VDD VSS
Valid Input
VREF = 50% VDD
Legend: tLH/tHL Max = Maximum Output Delay Specification tLH/tHL Min = Minimum Output Delay Specification tSU Min = Minimum Input Setup Specification tH Min = Minimum Input Hold Specification Note: See Table 5-7 "Drive Level and Measurement Points for AC Characteristics" on page 242 for VDD, VSS, and VREF values.
Figure 5-1. Test Measurements for AC Characteristics
pin Driver
CL
VSS
Figure 5-2. Test Circuit for AC Characteristics
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1/2 in. Max. PCI Driver pin
25
10pF
VSS
Figure 5-3. PCI Rising Edge (tLH) Test Circuit
1/2 in. Max. PCI Driver pin
VDD 10pF 25
VSS
Figure 5-4. PCI Falling Edge (tHL) Test Circuit
1/2 in. Max. PCI Driver pin
VDD 1 K 10pF 1 K
VSS
Figure 5-5. PCI Slew Rate Test Circuit
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Table 5-9. Clock and Reset Specifications
Symbol Parameter Min Max Duty Cycle Unit Comments (Note 1)
Output Signals
---
DCLK Frequency CLK_32K Frequency ISACLK Frequency
25
157.5 32.768 8.33333
40/60 50/50
MHz kHz MHz
Note 2 Note 3
--
Input Signals
--
CLK_14MHZ Frequency USBCLK Frequency TVCLK Frequency VID_CLK Frequency PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate
14.31818 48 27 135 30 11 11 1 4
45/55
MHz MHz MHz MHz ns ns ns V/ns See Figure 5-1 on page 243 and Figure 5-5 on page 244 (known as slewr/slewf), Note 5, and Note 6 Rising edge only (deassertion), Note 6 Note 4
---tCYC tHIGH tLOW --
-1. 2. 3. 4. 5. 6.
PCI_RST# Slew Rate
50
--
mV/ns
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF. Worst case duty cycle. Duty cycle is a function of PLL post divider. DCLK is programmable to standard video frequencies. Typical jitter < 650 ps peak-to-peak. CLK_14MHZ input jitter < 500 ps peak-to-peak. CLK_32K jitter = period of CLK_14MHZ. CLK_32K output frequency = CLK_14MHZ/436.95621. Frequency of operation is from DC to 33 MHz but at a single fixed frequency. Operation below 20 MHz is guaranteed by design. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 5-6. Not 100% tested.
tCYC tHIGH 0.6 VDD 0.5 VDD 0.4 VDD 0.3 VDD 0.2 VDD 0.4 VDD, peak-to-peak
(minimum)
tLOW
Figure 5-6. 3.3V PCICLK Waveform
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Table 5-10. DCLK PLL Specifications
Symbol fDCLK fREF tRISE/FALL -DC 1. Parameter DCLK Clock Operating Frequency Input Reference Frequency Output Clock Rise/Fall Time Jitter, Peak-to-Peak Duty Cycle -300 40/60 Min 25 14.318 2 300 60/40 Typ Max 157.5 Units MHz MHz ns ps % @ 25 MHz Comments (Note 1) Also known as CRT clock
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF.
Table 5-11. CPU Interface Timing
Symbol tSMI tSUSP# tSUSPASetup tSUSPAHold ---1. Parameter Rising PCICLK to SMI# Rising PCICLK to SUSP# SUSPA# Setup to Rising PCICLK SUSPA# Hold from Rising PCICLK IRQ13 Input INTR Output SMI# Output Min 3 6 0 3 Max 16 9 Units ns ns ns ns Comments (Note 1)
Asynchronous input for IRQ decode. Asynchronous output from IRQ decode. Asynchronous output from SMI decode.
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF.
PCICLK tSMI SMI# tSUSP SUSP# tSUSPAhold tSUSPAsetup SUSPA# Valid Input
Figure 5-7. CPU Interface Timing
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Table 5-12. Audio Interface Timing
Symbol tBITCLK tSDAT tSDATsetup tSDAThold 1. Parameter Rising BIT_CLK to SYNC Rising BIT_CLK to SDATA_OUT SDATA_IN setup to falling BIT_CLK SDATA_IN hold from falling BIT_CLK 10 10 Min Max 15 15 Units ns ns ns ns Comments (Note 1)
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF.
BIT_CLK tBITCLK SYNC tSDAT SDATA_OUT tSDAThold tSDATsetup SDATA_IN
Valid Input
Figure 5-8. Audio Interface Timing
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Table 5-13. USB Timing
Symbol Parameter Min Max Unit Comments (Note 1)
Full Speed Mode tR tF Rise Time Fall Time 4 4 20 20 ns ns
Low Speed Mode tR Rise Time 75 300 tF Fall Time 75 300 1. ns CL = 350 pF ns CL = 350 pF
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF.
Differential Buffer
Differential Data Lines VCRS
90% 10% 90% 10%
Rs TxD+
USB Driver
CL
tR
tF
Figure 5-9. USB Timing
Rs TxD-
VSS
USB Driver
CL
VSS
Figure 5-10. USB Test Circuit
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5.6 DISPLAY CHARACTERISTICS
* Display Miscellaneous Characteristics * CRT, TFT/TV and MPEG Display Timing Additionally, Figure 5-13 on page 252 is provided showing a typical video connection diagram. The following tables and figures describe the characteristics of the CRT, TFT/TV and MPEG Display interfaces. It is divided into the following categories: * CRT Display Recommended Operating Conditions * CRT Display Analog (DAC) Characteristics
Table 5-14. CRT Display Recommended Operating Conditions
Symbol AVDD RL IOUT RSET VEXTREF Parameter Power Supply connected to AVDD1, AVDD2 and AVDD3 Output Load on each of the pins IOUTR, IOUTG and IOUTB Output Current on each of the pins IOUTR, IOUTG and IOUTB Value of the full-scale adjust resistor connected to IREF External voltage reference connected to the EXTVREFIN pin 680 1.235 Min 3.14 Typ 3.3 37.5 21 Max 3.46 Units V Ohms mA Ohms V This resistor should have a 1% tolerance. R1, R2, and R3 as shown in Figure 5-13 on page 252 Comments
Table 5-15. CRT Display Analog (DAC) Characteristics
Symbol VOM VOC INL DNL tFS --tRISE tFALL 1. 2. 3. 4. Parameter Output Voltage Output Current Integral Linearity Error Differential Linearity Error Full Scale Settling Time DAC-to-DAC matching Power Supply Rejection Output Rise Time Output Fall Time Min Typ Max 0.735 20 +/-1 +/-1 2.5 5 0.7 3.8 3.8 Units V mA LSB LSB ns % % ns ns @ 1 KHz Note 2 and Note 3 Note 2 and Note 4 Comments (Note 1)
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF. Timing measurements are made with a 75 ohm doubly-terminated load, with VEXTREF = 1.235V and RSET = 680 ohms. 10% to 90% of full-scale transition. Full-scale transition: time from output minimum to maximum, not including clock and data feedthrough.
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Table 5-16. Display Miscellaneous Characteristics
Symbol Parameter White Level Relative to Black IAVDD AVDD Supply Current Min 16.74 Typ 17.62 60 Max 18.50 Units mA mA (Static) Comments
Table 5-17. CRT, TFT/TV and MPEG Display Timing
Symbol Setup/Hold Time tDisplaySetup Display Setup to Rising PCLK: VSYNC, HSYNC, ENA_DISP, FP_VSYNC, FP_HSYNC, PIXEL[23:0] Display Hold from Rising PCLK: VSYNC, HSYNC, ENA_DISP, FP_VSYNC, FP_HSYNC, PIXEL[23:0] VID_VAL Setup to Rising VID_CLK VID_VAL Hold from Rising VID_CLK VID_DATA Setup to Rising VID_CLK VID_DATA Hold from Rising VID_CLK 2.2 ns See Figure 5-1 on page 243. Parameter Min Typ Max Units Comments (Note 1)
tDisplayHold
1.0
ns
tVID_VALSetup tVID_VALHold tVID_DATASetup tVID_DATAHold Clock Specification tVID_CLKMin Delay Time FPOUTMinDelay, FPOUTMaxDelay
3.0 0.8 3.0 0.8
ns ns ns ns
See Figure 5-1 on page 243. See Figure 5-1 on page 243, Note 2
VID_CLK Minimum Clock Period
7.4
ns
TFT/TV Output Delays from FP_CLK: FP_DATA[17:0], FP_HSYNC_OUT, FP_VSYNC_OUT, FP_DISP_ENA_OUT, FP_ENA_VDD, FP_ENA_BKL, FP_CLK_EVEN VID_RDY Delay from Falling VID_CLK (early mode) VID_RDY delay from rising VID_CLK (normal mode)
0.5
4.5
ns
Note 3
VID_RDYMinDelayE, VID_RDYMaxDelayE VID_RDYMinDelayN, VID_RDYMaxDelayN 1. 2. 3. 4.
3.0 3.0
10.5 9.5
ns ns
Note 4
All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0C to 85C, and CL = 50 pF. Also applies to PIXEL[23:16] when in 16-bit video mode. All flat panel applications use the falling edge of FP_CLK to latch their data. The mode for VID_RDY (early or normal) is set with bit 25 of the Video Configuration Register (F4BAR+Memory Offset 00h[25]).
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FP_CLK FPOUTMaxDelay FPOUTMinDelay TFT/TV Outputs
Figure 5-11. Display TFT/TV Outputs Delays
VID_CLK VID_RDYMinDelayE VID_RDYMaxDelayE
VID_RDY (Early) VID_RDYMinDelayN VID_RDYMaxDelayN
VID_RDY (Normal)
Figure 5-12. MPEG Timing
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VDD AVDD L4 C7 EXTVREFIN VEXTREF C8 L5
VDD
IREF
RSET
AVSS IOUTR R1 AVSS IOUTG R2 AVSS IOUTB R3 AVSS C3 L3 C6 One-point ground C2 L2 C5 To RGB Video Connector C1 L1 C4
Legend
Part Designator R1-R3 RSET C1-C6 C7 C8 L1-L3 (Optional) L4-L5 (Optional) Value 75 Ohms, 1% 732 Ohms, 1% 33 pF 0.1 F, Ceramic 2.2 F, Electrolytic 120 Ohm Ferrite Bead 600 Ohm Ferrite Bead
Figure 5-13. Typical Video Connection Diagram
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1) 2)
Test Mode Information
The NAND tree test mode for board-level automatic test equipment (ATE). The I/O test mode for system design testing. form on SUSP# will toggle on each input change as shown in Figure 6-1. POR# is included as an input during the NAND Tree test, after being used to trigger the test first. IRQ7 (pin AD14) and TEST (pin D3) must be held high throughout the test.
The CS5530A provides two test modes:
6.1
NAND TREE TEST MODE
The NAND tree mode is used to test input and bidirectional pins which will be part of the NAND tree chain. Table 6-1 shows how to set the device for the NAND tree test. The output of the NAND tree is multiplexed on the SUSP# output (pin K26). After a POR# (pin K24) pulse, all inputs in Table 6-2 on page 254 are initialized to a "1" and then are successively pulled and held to a "0" starting with SUSP_3V (the first input pin in the tree). The output wave-
Table 6-1. NAND Tree Test Selection
Signal Name POR# TEST IRQ7 Pin No. K24 D3 AD14 Setting 0 -> 1 1 1
Example: Beginning of NAND Tree Test Sequence
Initial Conditions: TEST = 1, IRQ7 = 1, POR# = (first 0, then 1), all inputs `1'
SUSP_3V
SUSPA# NAND Tree Inputs PSERIAL
CLK_14MHZ
. . .
NAND Tree Output
SUSP# (out)
The following pins are not in the NAND tree: AEN, BALE, CPU_RST, DACK[3:0]#, DACK[7:5]#, DCLK, DDC_SCL, D+_PORT1, D-_PORT1, D+_PORT2, D-_PORT2, EXTVREFIN, FP_CLK, FP_CLK_EVEN, FP_DISP_ENA_OUT, FP_ENA_BKL, FP_ENA_VDD, FP_HSYNC_OUT, FP_VSYNC_OUT, GPCS#, GPORT_CS#, HSYNC_OUT, IDE_ADDR[2:0], IDE_CS[1:0]#, IDE_DACK[1:0]#, IDE_IOR[1:0]#, IDE_IOW[1:0]#, IDE_RST#, IOUTB, IOUTG, IOUTR, IREF, IRQ7, ISACLK, KBROMCS#, PC_BEEP, PCI_RST#, PLLTEST, SA_LATCH, SDATA_OUT, SMEMR#/RTCALE, SMEMW#/RTCCS#, SUSP#, SYNC, TEST, VID_RDY, VSYNC_OUT, all NCs, and all analog/digital supplies.
Figure 6-1. NAND Tree Output Waveform
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Table 6-2. NAND Tree Test Mode Pins
Signal Name SUSP_3V SUSPA# PSERIAL CLK_14MHZ SMI# INTR IRQ13 IDE_DATA7 IDE_DATA6 IDE_DATA8 IDE_DATA10 IDE_DATA5 IDE_DATA9 IDE_DATA11 IDE_DATA4 IDE_DATA12 IDE_DATA3 IDE_DATA1 IDE_DATA13 IDE_DATA2 IDE_DATA0 IDE_DATA14 IDE_DATA15 IDE_DREQ1 IDE_DREQ0 IDE_IORDY0 IDE_IORDY1 SA14/SD14 SA15/SD15 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 SA13/SD13 SA10/SD10 DRQ7 SA12/SD12 SA11/SD11 SA9/SD9 DRQ6 MEMW# MEMR# DRQ5 SA8/SD8 DRQ0 IRQ11 IRQ14 IRQ15 SBHE# IRQ12 Pin No. L24 L25 L26 P24 P25 P26 R23 U23 U24 V24 V25 W26 Y25 Y24 AA26 AA25 AB26 AA24 AB25 AB24 AC26 AC25 AB23 AC24 AD26 AD25 AE26 AD24 AE25 AC22 AE24 AF25 AF24 AD22 AC21 AE23 AF23 AE22 AC20 AF22 AE21 AF21 AD19 AE20 AF20 AE19 AD18 AF19 AE18 AF18 AC17 AD17 AE17 AF17 Signal Name IRQ10 IOCS16# MEMCS16# IRQ4 TC IRQ3 IRQ8# IRQ6 DRQ3 IRQ5 IRQ1 DRQ1 IOR# SA17 IOW# SA16 SA18 IOCHRDY SA19 DRQ2 ZEROWS# SA2/SD2 SA0/SD0 SA4/SD4 SA1/SD1 SA6/SD6 SA3/SD3 IRQ9 SA5/SD5 SA7/SD7 CLK_32K OVER_CUR# POWER_EN USBCLK BIT_CLK SDATA_IN DDC_SDA FP_DATA12 FP_DATA0 FP_DATA13 FP_DATA14 FP_DATA2 FP_DATA1 FP_DATA3 FP_DATA15 FP_DATA16 FP_DATA4 FP_DATA8 FP_DATA5 FP_DATA7 FP_DATA6 FP_DATA9 FP_DATA17 FP_DATA10 Pin No. AE16 AF16 AC15 AE15 AF15 AC14 AE14 AF14 AD13 AE13 AF13 AD12 AE12 AF12 AC11 AD11 AE11 AF11 AD10 AE10 AF10 AD9 AE9 AF6 AE6 AF5 AC6 AE5 AD5 AF4 AE3 W3 V4 W1 V2 U4 M4 L1 K3 K2 K1 J3 J2 J1 H2 H3 H1 G1 G2 G3 G4 F1 F3 E2 Signal Name FP_DATA11 FP_VSYNC FP_HSYNC ENA_DISP TVCLK PIXEL0 PIXEL3 PIXEL6 PIXEL4 PIXEL1 PIXEL2 PIXEL11 PIXEL9 PIXEL5 PIXEL7 HSYNC VSYNC PIXEL13 PIXEL14 PIXEL10 PIXEL8 VID_CLK PIXEL17 VID_VAL PIXEL12 PIXEL15 PIXEL20 PIXEL21 PIXEL16 PIXEL18 PIXEL19 PIXEL23 VID_DATA4 VID_DATA3 PIXEL22 VID_DATA0 VID_DATA7 VID_DATA6 VID_DATA5 VID_DATA1 VID_DATA2 PCLK AD1 INTD# INTA# INTB# INTC# AD3 AD0 AD2 AD5 AD7 AD4 AD6 Pin No. D1 C1 C2 B1 B2 A1 C4 D5 B3 A2 A3 C5 D6 B4 A4 C6 B5 D7 C7 A5 B6 A6 C8 B7 A7 B8 D9 C9 A8 B9 A9 C10 D11 C11 B11 A11 C12 B12 A12 C13 B13 A13 D14 B14 A14 D15 C15 B15 A15 C16 B16 A16 C17 B17 Signal Name AD9 AD8 C/BE0# AD12 AD11 AD10 AD15 AD14 AD13 PAR C/BE1# SERR# PERR# LOCK# DEVSEL# TRDY# FRAME# C/BE2# IRDY# AD17 AD18 AD16 GNT# AD21 AD19 AD22 AD20 AD26 C/BE3# AD23 AD25 STOP# AD24 AD27 AD28 AD29 AD31 AD30 HOLD_REQ# REQ# PCICLK POR# Pin No. A17 D18 B18 A18 B19 A19 A20 B20 C20 A21 B21 A22 B22 C22 A23 B23 C23 A24 B24 A25 B25 A26 D24 C25 B26 C26 E24 D25 D26 E25 G24 E26 F25 F26 G25 G26 H25 J24 H26 J25 J26 K24
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Test Mode Information (Continued)
6.2 I/O TEST
The following pins are INCLUDED in this test: * AD[31:0], AEN, BALE, C/BE[3:0]#, CLK_32K, CPU_RST, DACK[7:5,3:0], DDC_SCL, DDC_SDA, DEVSEL#, FP_CLK, FP_CLK_EVEN, FP_DATA[17:0], FP_DISP_ENA_OUT, FP_ENA_BKL, FP_ENA_VDD, FP_HSYNC_OUT, FP_VSYNC_OUT, FRAME#, GPCS#, GPIO[7:0], GPORT_CS#, HOLD_REQ#, HSYNC_OUT, IDE_ADDR[2:0], IDE_CS[1:0]#, IDE_DACK[1:0]#, IDE_DATA[15:0], IDE_IOR[1:0]#, IDE_IOW[1:0]#, IDE_RST#, INTR, IOCHRDY, IOR#, IOW#, IRDY#, ISACLK, KBROMCS#, LOCK#, MEMCS16#, MEMR#, MEMW#, PAR, PCI_RST#, PC_BEEP, PERR#, POWER_EN, REQ#, SA/SD[15:0], SA[19:16], SA_LATCH, SBHE#, SDATA_OUT, SERR#, SMEMR#, SMEMW#, SMI#, STOP#, SUSP#, SUSP_3V, SYNC, TC, TRDY#, VID_RDY, VSYNC_OUT Note: The SA/SD and SA bus, IOR#, IOW#, MEMR#, MEMW# and SBHE# pins never actually float, because they have internal weak pull-up devices that remain active. This test affects all output and bidirectional pins. To trigger the I/O test, set the TEST and IRQ[3:7] pins according to Table 6-3, while holding POR# low. The test begins when POR# is brought high. Starting with the next rising edge of PCICLK, the states listed in Table 6-4 are entered by all digital output and I/O pins on successive PCICLK pulses:
Table 6-3. I/O Test Selection
Signal Name POR# TEST IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Pin No. K24 D3 AC14 AE15 AE13 AF14 AD14 Setting X 1 0 1 1 0 1
The following pins are EXCLUDED from this test:
Table 6-4. I/O Test Sequence
Clock # Before 1 1 2 3 4 5 6 7 8 and beyond Output Pin States Undefined Floating High Low Floating Low High Floating Undefined
* Input-only pins: BIT_CLK, CLK_14MHZ, DRQ[7:5,3:0], ENA_DISP, FP_HSYNC, FP_VSYNC, GNT#, HSYNC, IDE_DREQ[1:0], IDE_IORDY[1:0], INTA#, INTB#, INTC#, INTD#, IOCS16#, IRQ1, IRQ[7:3], IRQ8#, IRQ[15:9], OVER_CUR#, PCICLK, PCLK, PIXEL[23:0], POR#, PSERIAL, SDATA_IN, SUSPA#, TEST, TVCLK, USBCLK, VID_CLK, VID_DATA[7:0], VID_VAL, VSYNC, ZEROWS#. * USB pins: D+_PORT1, D-_PORT1, D+_PORT2, D-_PORT2, AVDD_USB, AVSS_USB. * Time-critical output: DCLK. * Analog pins (including supplies): EXTVREFIN, IOUTB, IOUTG, IOUTR, IREF, PLLAGD, PLLDGN, PLLDVD, PLLTEST, AVDDx, AVSSx. * Digital supply pins (VDD, VSS) and No Connects (NC).
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7.0
Physical Dimensions
The physical dimensions for the 352 PBGA (Plastic Ball Grid Array) package for the Geode CS5530A are provided in Figure 7-1.
Figure 7-1. 352 PBGA Mechanical Package Outline
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Appendix A
Support Documentation
A.1 REVISION HISTORY
This document is a report of the revision/creation process of the architectural specification for the CS5530A I/O Companion. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below.
Table A-1. Revision History
Revision # (PDF Date) 0.1 (4/2/00) Revisions / Comments Completed formatting first-pass of spec. Current spec is updated version of CS5530 data book with additional inputs from engineering. Differences between this spec's revision and the CS5530 data book are denoted with a change bar in the margin. Still need to proof-read for "ripple effects" made by engineering changes for next rev. Corrections from Issues 1.3. Further corrections from Issues 1.3. Partly indexed. Corrections from Issues 1.3 and 1.5. Some issues remain to be resolved. Index markers inserted through AT chapter. TME/Tech Pubs edits. See document revision 0.5 for revision history. TME/Tech Pubs edits. See document revision 0.6 for revision history details. TME/Tech Pubs/Engr edits. See document revision 0.7 for revision history details. Note: 1.0 (11/10/00) Next revision to include section on "recommended soldering parameters" in Section 7.0 "Physical Dimensions".
0.2 (6/16/00) 0.3 (6/27/00) 0.4 (7/5/00) 0.5 (7/19/00) 0.6 (8/7/00) 0.7(9/18/00)
TME/Tech Pubs/Engr edits. See document revision 1.0 for revision history details. Note: Will create separate applications note on "recommended soldering parameters" as opposed to adding as subsection in data book.
1.1 (5/1/01)
TME/Engr edits. See Table A-2 for details. Note: Will not create separate applications note on "recommended soldering parameters". Applications is fulfilling any customer inquiries with a document supplied by National's Quality Group.
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Support Documentation (Continued)
Table A-2. Edits to Create Revision 1.1
Section Description
Section 2.0 "Signal Definitions" Section 2.2.2 "Clock Interface" * Changed last sentence of DCLK signal description on page 23. Did say: "However, system constraints limit DCLK to 150 MHz when DCLK is used as the graphics subsystem clock." Now says: "However, when DCLK is used as the graphics subsystem clock, the Geode processor determines the maximum DCLK frequency." * Changed resistor value in IREF signal description (from 732 ohm to 680 ohm) on page 36.
Section 2.2.11 "Display Interface"
Section 3.8 "Display Subsystem Extensions" Section 3.8.3 "Video Overlay" * Added sentence to last paragraph on page 135: -- "However, system maximum resolution is not determined by the CS5530A since it is not the source of the graphics data and timings." * Section 3.8.5.3 "Flat Panel Support" on page 137 -- Added subsection titled "Flat Panel Power-Up/Down Sequence". Section 5.0 "Electrical Specifications" Section 5.5 "AC Characteristics" * Table 5-8 "AC Characteristics" on page 242: -- Removed 8 mA, DOTCLK, and FP_CLK tLH and tHL parameters. * Table 5-10 "DCLK PLL Specifications" on page 246: -- Removed Jitter, Sigma One parameter from table (completely). * Table 5-11 "CPU Interface Timing" on page 246: -- Changed tSMI max value from 9 ns to 16 ns. -- Changed tSUSPAHold min value from 1 ns to 3 ns. * Table 5-15 "CRT Display Analog (DAC) Characteristics" on page 249: -- Added VOM max value of 0.735V. -- Added VOC max value of 20 mA. -- Added tFS max value of 2.5 ns. -- Removed COUT parameter from table (completely). -- Changed tRISE max value from 3 to 3.8 ns. -- Added tFALL max value of 3.8 ns. -- Changed RSET value in Note 2 from 732 ohms to 680 ohms. * Table 5-17 "CRT, TFT/TV and MPEG Display Timing" on page 250: -- Changed tDisplaySetup min value from 2.5 ns to 2.2 ns. -- Changed tVID_VALSetup min value from 3.75 ns to 3.0 ns. -- Changed tVID_VALHold min value from 0 ns to 0.8 ns. -- Changed tVID_DATASetup min value from 3.75 ns to 3.0 ns. -- Changed tVID_DATAHold min value from 0 ns to 0.8 ns. -- Changed tVID_CLKMin parameter description from "VID_CLK Minimum Pulse Width" to "VID_CLK Minimum Clock Period". -- Changed FPOUTMinDelay, FPOUTMaxDelay min value from 0.1 ns to 0.5 and max value from 5.2 ns to 4.5 ns.
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LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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